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265 lines
10 KiB
Verilog
265 lines
10 KiB
Verilog
/*
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Copyright (c) 2021-2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream pipeline FIFO
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*/
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module axis_pipeline_fifo #
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(
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// Width of AXI stream interfaces in bits
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parameter DATA_WIDTH = 8,
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// Propagate tkeep signal
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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// tkeep signal width (words per cycle)
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parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
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// Propagate tlast signal
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parameter LAST_ENABLE = 1,
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// Propagate tid signal
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parameter ID_ENABLE = 0,
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// tid signal width
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parameter ID_WIDTH = 8,
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// Propagate tdest signal
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parameter DEST_ENABLE = 0,
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// tdest signal width
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parameter DEST_WIDTH = 8,
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// Propagate tuser signal
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parameter USER_ENABLE = 1,
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// tuser signal width
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parameter USER_WIDTH = 1,
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// Number of registers in pipeline
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parameter LENGTH = 2
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] s_axis_tdata,
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input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [ID_WIDTH-1:0] s_axis_tid,
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input wire [DEST_WIDTH-1:0] s_axis_tdest,
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input wire [USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] m_axis_tdata,
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output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [ID_WIDTH-1:0] m_axis_tid,
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output wire [DEST_WIDTH-1:0] m_axis_tdest,
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output wire [USER_WIDTH-1:0] m_axis_tuser
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);
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parameter FIFO_ADDR_WIDTH = LENGTH < 2 ? 3 : $clog2(LENGTH*4+1);
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wire [DATA_WIDTH-1:0] axis_tdata_pipe[0:LENGTH];
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wire [KEEP_WIDTH-1:0] axis_tkeep_pipe[0:LENGTH];
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wire axis_tvalid_pipe[0:LENGTH];
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wire axis_tready_pipe[0:LENGTH];
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wire axis_tlast_pipe[0:LENGTH];
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wire [ID_WIDTH-1:0] axis_tid_pipe[0:LENGTH];
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wire [DEST_WIDTH-1:0] axis_tdest_pipe[0:LENGTH];
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wire [USER_WIDTH-1:0] axis_tuser_pipe[0:LENGTH];
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generate
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genvar n;
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for (n = 0; n < LENGTH; n = n + 1) begin : stage
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(* shreg_extract = "no" *)
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reg [DATA_WIDTH-1:0] axis_tdata_reg = 0;
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(* shreg_extract = "no" *)
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reg [KEEP_WIDTH-1:0] axis_tkeep_reg = 0;
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(* shreg_extract = "no" *)
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reg axis_tvalid_reg = 0;
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(* shreg_extract = "no" *)
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reg axis_tready_reg = 0;
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(* shreg_extract = "no" *)
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reg axis_tlast_reg = 0;
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(* shreg_extract = "no" *)
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reg [ID_WIDTH-1:0] axis_tid_reg = 0;
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(* shreg_extract = "no" *)
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reg [DEST_WIDTH-1:0] axis_tdest_reg = 0;
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(* shreg_extract = "no" *)
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reg [USER_WIDTH-1:0] axis_tuser_reg = 0;
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assign axis_tdata_pipe[n+1] = axis_tdata_reg;
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assign axis_tkeep_pipe[n+1] = axis_tkeep_reg;
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assign axis_tvalid_pipe[n+1] = axis_tvalid_reg;
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assign axis_tlast_pipe[n+1] = axis_tlast_reg;
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assign axis_tid_pipe[n+1] = axis_tid_reg;
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assign axis_tdest_pipe[n+1] = axis_tdest_reg;
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assign axis_tuser_pipe[n+1] = axis_tuser_reg;
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assign axis_tready_pipe[n] = axis_tready_reg;
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always @(posedge clk) begin
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axis_tdata_reg <= axis_tdata_pipe[n];
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axis_tkeep_reg <= axis_tkeep_pipe[n];
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axis_tvalid_reg <= axis_tvalid_pipe[n];
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axis_tlast_reg <= axis_tlast_pipe[n];
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axis_tid_reg <= axis_tid_pipe[n];
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axis_tdest_reg <= axis_tdest_pipe[n];
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axis_tuser_reg <= axis_tuser_pipe[n];
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axis_tready_reg <= axis_tready_pipe[n+1];
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if (rst) begin
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axis_tvalid_reg <= 1'b0;
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axis_tready_reg <= 1'b0;
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end
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end
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end
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if (LENGTH > 0) begin : fifo
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assign axis_tdata_pipe[0] = s_axis_tdata;
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assign axis_tkeep_pipe[0] = s_axis_tkeep;
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assign axis_tvalid_pipe[0] = s_axis_tvalid & s_axis_tready;
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assign axis_tlast_pipe[0] = s_axis_tlast;
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assign axis_tid_pipe[0] = s_axis_tid;
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assign axis_tdest_pipe[0] = s_axis_tdest;
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assign axis_tuser_pipe[0] = s_axis_tuser;
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assign s_axis_tready = axis_tready_pipe[0];
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wire [DATA_WIDTH-1:0] m_axis_tdata_int = axis_tdata_pipe[LENGTH];
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wire [KEEP_WIDTH-1:0] m_axis_tkeep_int = axis_tkeep_pipe[LENGTH];
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wire m_axis_tvalid_int = axis_tvalid_pipe[LENGTH];
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wire m_axis_tready_int;
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wire m_axis_tlast_int = axis_tlast_pipe[LENGTH];
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wire [ID_WIDTH-1:0] m_axis_tid_int = axis_tid_pipe[LENGTH];
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wire [DEST_WIDTH-1:0] m_axis_tdest_int = axis_tdest_pipe[LENGTH];
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wire [USER_WIDTH-1:0] m_axis_tuser_int = axis_tuser_pipe[LENGTH];
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assign axis_tready_pipe[LENGTH] = m_axis_tready_int;
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// output datapath logic
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reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg m_axis_tvalid_reg = 1'b0;
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reg m_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
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reg [FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
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reg [FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
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reg out_fifo_half_full_reg = 1'b0;
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wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {FIFO_ADDR_WIDTH{1'b0}}});
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wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [DATA_WIDTH-1:0] out_fifo_tdata[2**FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg out_fifo_tlast[2**FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [ID_WIDTH-1:0] out_fifo_tid[2**FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [DEST_WIDTH-1:0] out_fifo_tdest[2**FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [USER_WIDTH-1:0] out_fifo_tuser[2**FIFO_ADDR_WIDTH-1:0];
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assign m_axis_tready_int = !out_fifo_half_full_reg;
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assign m_axis_tdata = m_axis_tdata_reg;
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assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
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assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
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assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
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always @(posedge clk) begin
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m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready;
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out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(FIFO_ADDR_WIDTH-1);
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if (!out_fifo_full && m_axis_tvalid_int) begin
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out_fifo_tdata[out_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_int;
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out_fifo_tkeep[out_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_int;
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out_fifo_tlast[out_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_int;
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out_fifo_tid[out_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_int;
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out_fifo_tdest[out_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_int;
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out_fifo_tuser[out_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_int;
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out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
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end
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if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready)) begin
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m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
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m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
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m_axis_tvalid_reg <= 1'b1;
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m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
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m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
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m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
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m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
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out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
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end
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if (rst) begin
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out_fifo_wr_ptr_reg <= 0;
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out_fifo_rd_ptr_reg <= 0;
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m_axis_tvalid_reg <= 1'b0;
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end
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end
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end else begin
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// bypass
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assign m_axis_tdata = s_axis_tdata;
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assign m_axis_tkeep = KEEP_ENABLE ? s_axis_tkeep : {KEEP_WIDTH{1'b1}};
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assign m_axis_tvalid = s_axis_tvalid;
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assign m_axis_tlast = LAST_ENABLE ? s_axis_tlast : 1'b1;
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assign m_axis_tid = ID_ENABLE ? s_axis_tid : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? s_axis_tdest : {DEST_WIDTH{1'b0}};
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assign m_axis_tuser = USER_ENABLE ? s_axis_tuser : {USER_WIDTH{1'b0}};
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assign s_axis_tready = m_axis_tready;
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end
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endgenerate
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endmodule
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`resetall
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