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corundum/fpga/common
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Alex Forencich 03a49d7bc6 Add 25G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-19 23:43:22 -07:00
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rtl
Add 25G mqnic design for DE10-Agilex
2022-07-19 23:43:22 -07:00
syn/vivado
Use PHY rx_status signal for link status detection
2022-05-17 00:46:05 -07:00
tb
Add mqnic core logic for Intel P-Tile
2022-07-18 23:15:54 -07:00
lib
Add symlink
2019-08-11 00:33:22 -07:00