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corundum/fpga/mqnic/AU200/fpga_25g/rtl
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Alex Forencich 9963674c61 Add flow control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-09-09 19:01:36 -07:00
..
common
Unified 10G/25G design for AU200
2022-03-14 21:38:31 -07:00
debounce_switch.v
Unified 10G/25G design for AU200
2022-03-14 21:38:31 -07:00
fpga_core.v
Add flow control
2023-09-09 19:01:36 -07:00
fpga.v
Add flow control
2023-09-09 19:01:36 -07:00
sync_signal.v
Unified 10G/25G design for AU200
2022-03-14 21:38:31 -07:00