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corundum/example/ExaNIC_X10/fpga/rtl
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Alex Forencich 9297c518f1 Add example design for ExaNIC X10
2021-11-03 18:10:17 -07:00
..
common
Add example design for ExaNIC X10
2021-11-03 18:10:17 -07:00
fpga_core.v
Add example design for ExaNIC X10
2021-11-03 18:10:17 -07:00
fpga.v
Add example design for ExaNIC X10
2021-11-03 18:10:17 -07:00
sync_reset.v
Add example design for ExaNIC X10
2021-11-03 18:10:17 -07:00
sync_signal.v
Add example design for ExaNIC X10
2021-11-03 18:10:17 -07:00