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515 lines
18 KiB
Verilog
515 lines
18 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream asynchronous FIFO
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*/
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module axis_async_fifo #
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(
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parameter DEPTH = 4096,
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter LAST_ENABLE = 1,
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1,
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parameter FRAME_FIFO = 0,
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parameter USER_BAD_FRAME_VALUE = 1'b1,
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parameter USER_BAD_FRAME_MASK = 1'b1,
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parameter DROP_BAD_FRAME = 0,
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parameter DROP_WHEN_FULL = 0
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)
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(
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/*
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* Common asynchronous reset
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*/
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input wire async_rst,
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/*
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* AXI input
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*/
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input wire s_clk,
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input wire [DATA_WIDTH-1:0] s_axis_tdata,
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input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [ID_WIDTH-1:0] s_axis_tid,
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input wire [DEST_WIDTH-1:0] s_axis_tdest,
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input wire [USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI output
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*/
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input wire m_clk,
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output wire [DATA_WIDTH-1:0] m_axis_tdata,
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output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [ID_WIDTH-1:0] m_axis_tid,
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output wire [DEST_WIDTH-1:0] m_axis_tdest,
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output wire [USER_WIDTH-1:0] m_axis_tuser,
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/*
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* Status
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*/
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output wire s_status_overflow,
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output wire s_status_bad_frame,
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output wire s_status_good_frame,
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output wire m_status_overflow,
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output wire m_status_bad_frame,
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output wire m_status_good_frame
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);
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parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
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// check configuration
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initial begin
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if (FRAME_FIFO && !LAST_ENABLE) begin
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$error("Error: FRAME_FIFO set requires LAST_ENABLE set");
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$finish;
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end
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if (DROP_BAD_FRAME && !FRAME_FIFO) begin
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$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set");
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$finish;
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end
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if (DROP_WHEN_FULL && !FRAME_FIFO) begin
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$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set");
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$finish;
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end
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if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
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$error("Error: Invalid USER_BAD_FRAME_MASK value");
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$finish;
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end
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end
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localparam KEEP_OFFSET = DATA_WIDTH;
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localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
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localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
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localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
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localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
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localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
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reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
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reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
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reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
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reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_sync_gray_next;
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reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_gray_next;
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reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
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reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
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reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
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reg wr_ptr_update_valid_reg = 1'b0, wr_ptr_update_valid_next;
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reg wr_ptr_update_reg = 1'b0, wr_ptr_update_next;
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reg wr_ptr_update_sync1_reg = 1'b0;
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reg wr_ptr_update_sync2_reg = 1'b0;
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reg wr_ptr_update_sync3_reg = 1'b0;
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reg wr_ptr_update_ack_sync1_reg = 1'b0;
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reg wr_ptr_update_ack_sync2_reg = 1'b0;
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reg s_rst_sync1_reg = 1'b1;
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reg s_rst_sync2_reg = 1'b1;
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reg s_rst_sync3_reg = 1'b1;
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reg m_rst_sync1_reg = 1'b1;
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reg m_rst_sync2_reg = 1'b1;
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reg m_rst_sync3_reg = 1'b1;
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reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
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reg [WIDTH-1:0] mem_read_data_reg;
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reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
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wire [WIDTH-1:0] s_axis;
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reg [WIDTH-1:0] m_axis_reg;
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reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
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// full when first TWO MSBs do NOT match, but rest matches
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// (gray code equivalent of first MSB different but rest same)
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wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
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(wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
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(wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
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wire full_cur = ((wr_ptr_cur_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
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(wr_ptr_cur_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
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(wr_ptr_cur_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
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// empty when pointers match exactly
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wire empty = rd_ptr_gray_reg == (FRAME_FIFO ? wr_ptr_gray_sync1_reg : wr_ptr_gray_sync2_reg);
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// overflow within packet
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wire full_wr = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) &&
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(wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0]));
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// control signals
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reg write;
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reg read;
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reg store_output;
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reg drop_frame_reg = 1'b0, drop_frame_next;
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reg overflow_reg = 1'b0, overflow_next;
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reg bad_frame_reg = 1'b0, bad_frame_next;
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reg good_frame_reg = 1'b0, good_frame_next;
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reg overflow_sync1_reg = 1'b0;
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reg overflow_sync2_reg = 1'b0;
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reg overflow_sync3_reg = 1'b0;
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reg overflow_sync4_reg = 1'b0;
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reg bad_frame_sync1_reg = 1'b0;
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reg bad_frame_sync2_reg = 1'b0;
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reg bad_frame_sync3_reg = 1'b0;
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reg bad_frame_sync4_reg = 1'b0;
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reg good_frame_sync1_reg = 1'b0;
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reg good_frame_sync2_reg = 1'b0;
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reg good_frame_sync3_reg = 1'b0;
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reg good_frame_sync4_reg = 1'b0;
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assign s_axis_tready = (FRAME_FIFO ? (!full_cur || full_wr || DROP_WHEN_FULL) : !full) && !s_rst_sync3_reg;
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generate
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assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
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if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
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if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
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if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid;
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if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
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if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser;
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endgenerate
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assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tdata = m_axis_reg[DATA_WIDTH-1:0];
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assign m_axis_tkeep = KEEP_ENABLE ? m_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
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assign m_axis_tlast = LAST_ENABLE ? m_axis_reg[LAST_OFFSET] : 1'b1;
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assign m_axis_tid = ID_ENABLE ? m_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
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assign m_axis_tuser = USER_ENABLE ? m_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
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assign s_status_overflow = overflow_reg;
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assign s_status_bad_frame = bad_frame_reg;
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assign s_status_good_frame = good_frame_reg;
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assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg;
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assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg;
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assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg;
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// reset synchronization
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always @(posedge s_clk or posedge async_rst) begin
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if (async_rst) begin
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s_rst_sync1_reg <= 1'b1;
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s_rst_sync2_reg <= 1'b1;
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s_rst_sync3_reg <= 1'b1;
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end else begin
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s_rst_sync1_reg <= 1'b0;
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s_rst_sync2_reg <= s_rst_sync1_reg || m_rst_sync1_reg;
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s_rst_sync3_reg <= s_rst_sync2_reg;
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end
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end
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always @(posedge m_clk or posedge async_rst) begin
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if (async_rst) begin
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m_rst_sync1_reg <= 1'b1;
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m_rst_sync2_reg <= 1'b1;
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m_rst_sync3_reg <= 1'b1;
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end else begin
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m_rst_sync1_reg <= 1'b0;
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m_rst_sync2_reg <= s_rst_sync1_reg || m_rst_sync1_reg;
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m_rst_sync3_reg <= m_rst_sync2_reg;
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end
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end
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// Write logic
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always @* begin
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write = 1'b0;
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drop_frame_next = 1'b0;
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overflow_next = 1'b0;
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bad_frame_next = 1'b0;
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good_frame_next = 1'b0;
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wr_ptr_next = wr_ptr_reg;
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wr_ptr_cur_next = wr_ptr_cur_reg;
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wr_ptr_gray_next = wr_ptr_gray_reg;
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wr_ptr_sync_gray_next = wr_ptr_sync_gray_reg;
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wr_ptr_cur_gray_next = wr_ptr_cur_gray_reg;
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wr_ptr_update_valid_next = wr_ptr_update_valid_reg;
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wr_ptr_update_next = wr_ptr_update_reg;
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if (FRAME_FIFO && wr_ptr_update_valid_reg) begin
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// have updated pointer to sync
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if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin
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// no sync in progress; sync update
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wr_ptr_update_valid_next = 1'b0;
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wr_ptr_sync_gray_next = wr_ptr_gray_reg;
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wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg;
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end
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end
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if (s_axis_tready && s_axis_tvalid) begin
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// transfer in
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if (!FRAME_FIFO) begin
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// normal FIFO mode
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write = 1'b1;
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wr_ptr_next = wr_ptr_reg + 1;
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wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
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end else if (full_cur || full_wr || drop_frame_reg) begin
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// full, packet overflow, or currently dropping frame
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// drop frame
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drop_frame_next = 1'b1;
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if (s_axis_tlast) begin
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// end of frame, reset write pointer
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wr_ptr_cur_next = wr_ptr_reg;
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wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1);
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drop_frame_next = 1'b0;
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overflow_next = 1'b1;
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end
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end else begin
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write = 1'b1;
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wr_ptr_cur_next = wr_ptr_cur_reg + 1;
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wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1);
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if (s_axis_tlast) begin
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// end of frame
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if (DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
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// bad packet, reset write pointer
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wr_ptr_cur_next = wr_ptr_reg;
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wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1);
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bad_frame_next = 1'b1;
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end else begin
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// good packet, update write pointer
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wr_ptr_next = wr_ptr_cur_reg + 1;
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wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
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if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin
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// no sync in progress; sync update
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wr_ptr_update_valid_next = 1'b0;
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wr_ptr_sync_gray_next = wr_ptr_gray_next;
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wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg;
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end else begin
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// sync in progress; flag it for later
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wr_ptr_update_valid_next = 1'b1;
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end
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good_frame_next = 1'b1;
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end
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end
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end
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end
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end
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always @(posedge s_clk) begin
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if (s_rst_sync3_reg) begin
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wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_update_valid_reg <= 1'b0;
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wr_ptr_update_reg <= 1'b0;
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drop_frame_reg <= 1'b0;
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overflow_reg <= 1'b0;
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bad_frame_reg <= 1'b0;
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good_frame_reg <= 1'b0;
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end else begin
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wr_ptr_reg <= wr_ptr_next;
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wr_ptr_cur_reg <= wr_ptr_cur_next;
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wr_ptr_gray_reg <= wr_ptr_gray_next;
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wr_ptr_sync_gray_reg <= wr_ptr_sync_gray_next;
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wr_ptr_cur_gray_reg <= wr_ptr_cur_gray_next;
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wr_ptr_update_valid_reg <= wr_ptr_update_valid_next;
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wr_ptr_update_reg <= wr_ptr_update_next;
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drop_frame_reg <= drop_frame_next;
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overflow_reg <= overflow_next;
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bad_frame_reg <= bad_frame_next;
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good_frame_reg <= good_frame_next;
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end
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if (FRAME_FIFO) begin
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wr_addr_reg <= wr_ptr_cur_next;
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end else begin
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wr_addr_reg <= wr_ptr_next;
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end
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if (write) begin
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mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= s_axis;
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end
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end
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// pointer synchronization
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always @(posedge s_clk) begin
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if (s_rst_sync3_reg) begin
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rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
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rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_update_ack_sync1_reg <= 1'b0;
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wr_ptr_update_ack_sync2_reg <= 1'b0;
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end else begin
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rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
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rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
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wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
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wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
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end
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end
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always @(posedge m_clk) begin
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if (m_rst_sync3_reg) begin
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wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_update_sync1_reg <= 1'b0;
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wr_ptr_update_sync2_reg <= 1'b0;
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wr_ptr_update_sync3_reg <= 1'b0;
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end else begin
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if (!FRAME_FIFO) begin
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wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
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end else if (wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin
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wr_ptr_gray_sync1_reg <= wr_ptr_sync_gray_reg;
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end
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wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
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wr_ptr_update_sync1_reg <= wr_ptr_update_reg;
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wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
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wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
|
|
end
|
|
end
|
|
|
|
// status synchronization
|
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always @(posedge s_clk) begin
|
|
if (s_rst_sync3_reg) begin
|
|
overflow_sync1_reg <= 1'b0;
|
|
bad_frame_sync1_reg <= 1'b0;
|
|
good_frame_sync1_reg <= 1'b0;
|
|
end else begin
|
|
overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg;
|
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bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg;
|
|
good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg;
|
|
end
|
|
end
|
|
|
|
always @(posedge m_clk) begin
|
|
if (m_rst_sync3_reg) begin
|
|
overflow_sync2_reg <= 1'b0;
|
|
overflow_sync3_reg <= 1'b0;
|
|
overflow_sync4_reg <= 1'b0;
|
|
bad_frame_sync2_reg <= 1'b0;
|
|
bad_frame_sync3_reg <= 1'b0;
|
|
bad_frame_sync4_reg <= 1'b0;
|
|
good_frame_sync2_reg <= 1'b0;
|
|
good_frame_sync3_reg <= 1'b0;
|
|
good_frame_sync4_reg <= 1'b0;
|
|
end else begin
|
|
overflow_sync2_reg <= overflow_sync1_reg;
|
|
overflow_sync3_reg <= overflow_sync2_reg;
|
|
overflow_sync4_reg <= overflow_sync3_reg;
|
|
bad_frame_sync2_reg <= bad_frame_sync1_reg;
|
|
bad_frame_sync3_reg <= bad_frame_sync2_reg;
|
|
bad_frame_sync4_reg <= bad_frame_sync3_reg;
|
|
good_frame_sync2_reg <= good_frame_sync1_reg;
|
|
good_frame_sync3_reg <= good_frame_sync2_reg;
|
|
good_frame_sync4_reg <= good_frame_sync3_reg;
|
|
end
|
|
end
|
|
|
|
// Read logic
|
|
always @* begin
|
|
read = 1'b0;
|
|
|
|
rd_ptr_next = rd_ptr_reg;
|
|
rd_ptr_gray_next = rd_ptr_gray_reg;
|
|
|
|
mem_read_data_valid_next = mem_read_data_valid_reg;
|
|
|
|
if (store_output || !mem_read_data_valid_reg) begin
|
|
// output data not valid OR currently being transferred
|
|
if (!empty) begin
|
|
// not empty, perform read
|
|
read = 1'b1;
|
|
mem_read_data_valid_next = 1'b1;
|
|
rd_ptr_next = rd_ptr_reg + 1;
|
|
rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1);
|
|
end else begin
|
|
// empty, invalidate
|
|
mem_read_data_valid_next = 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge m_clk) begin
|
|
if (m_rst_sync3_reg) begin
|
|
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
|
|
rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
|
|
mem_read_data_valid_reg <= 1'b0;
|
|
end else begin
|
|
rd_ptr_reg <= rd_ptr_next;
|
|
rd_ptr_gray_reg <= rd_ptr_gray_next;
|
|
mem_read_data_valid_reg <= mem_read_data_valid_next;
|
|
end
|
|
|
|
rd_addr_reg <= rd_ptr_next;
|
|
|
|
if (read) begin
|
|
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
|
|
end
|
|
end
|
|
|
|
// Output register
|
|
always @* begin
|
|
store_output = 1'b0;
|
|
|
|
m_axis_tvalid_next = m_axis_tvalid_reg;
|
|
|
|
if (m_axis_tready || !m_axis_tvalid) begin
|
|
store_output = 1'b1;
|
|
m_axis_tvalid_next = mem_read_data_valid_reg;
|
|
end
|
|
end
|
|
|
|
always @(posedge m_clk) begin
|
|
if (m_rst_sync3_reg) begin
|
|
m_axis_tvalid_reg <= 1'b0;
|
|
end else begin
|
|
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
|
end
|
|
|
|
if (store_output) begin
|
|
m_axis_reg <= mem_read_data_reg;
|
|
end
|
|
end
|
|
|
|
endmodule
|