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229 lines
7.3 KiB
Verilog
229 lines
7.3 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 lite clock domain crossing module (write)
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*/
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module axil_cdc_wr #
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(
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// Width of data bus in bits
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parameter DATA_WIDTH = 32,
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_WIDTH = (DATA_WIDTH/8)
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)
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(
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/*
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* AXI lite slave interface
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*/
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input wire s_clk,
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input wire s_rst,
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input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
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input wire [2:0] s_axil_awprot,
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input wire s_axil_awvalid,
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output wire s_axil_awready,
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input wire [DATA_WIDTH-1:0] s_axil_wdata,
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input wire [STRB_WIDTH-1:0] s_axil_wstrb,
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input wire s_axil_wvalid,
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output wire s_axil_wready,
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output wire [1:0] s_axil_bresp,
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output wire s_axil_bvalid,
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input wire s_axil_bready,
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/*
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* AXI lite master interface
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*/
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input wire m_clk,
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input wire m_rst,
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output wire [ADDR_WIDTH-1:0] m_axil_awaddr,
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output wire [2:0] m_axil_awprot,
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output wire m_axil_awvalid,
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input wire m_axil_awready,
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output wire [DATA_WIDTH-1:0] m_axil_wdata,
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output wire [STRB_WIDTH-1:0] m_axil_wstrb,
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output wire m_axil_wvalid,
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input wire m_axil_wready,
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input wire [1:0] m_axil_bresp,
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input wire m_axil_bvalid,
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output wire m_axil_bready
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);
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reg [1:0] s_state_reg = 2'd0;
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reg s_flag_reg = 1'b0;
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(* srl_style = "register" *)
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reg s_flag_sync_reg_1 = 1'b0;
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(* srl_style = "register" *)
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reg s_flag_sync_reg_2 = 1'b0;
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reg [1:0] m_state_reg = 2'd0;
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reg m_flag_reg = 1'b0;
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(* srl_style = "register" *)
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reg m_flag_sync_reg_1 = 1'b0;
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(* srl_style = "register" *)
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reg m_flag_sync_reg_2 = 1'b0;
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reg [ADDR_WIDTH-1:0] s_axil_awaddr_reg = {ADDR_WIDTH{1'b0}};
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reg [2:0] s_axil_awprot_reg = 3'd0;
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reg s_axil_awvalid_reg = 1'b0;
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reg [DATA_WIDTH-1:0] s_axil_wdata_reg = {DATA_WIDTH{1'b0}};
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reg [STRB_WIDTH-1:0] s_axil_wstrb_reg = {STRB_WIDTH{1'b0}};
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reg s_axil_wvalid_reg = 1'b0;
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reg [1:0] s_axil_bresp_reg = 2'b00;
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reg s_axil_bvalid_reg = 1'b0;
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reg [ADDR_WIDTH-1:0] m_axil_awaddr_reg = {ADDR_WIDTH{1'b0}};
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reg [2:0] m_axil_awprot_reg = 3'd0;
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reg m_axil_awvalid_reg = 1'b0;
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reg [DATA_WIDTH-1:0] m_axil_wdata_reg = {DATA_WIDTH{1'b0}};
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reg [STRB_WIDTH-1:0] m_axil_wstrb_reg = {STRB_WIDTH{1'b0}};
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reg m_axil_wvalid_reg = 1'b0;
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reg [1:0] m_axil_bresp_reg = 2'b00;
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reg m_axil_bvalid_reg = 1'b1;
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assign s_axil_awready = !s_axil_awvalid_reg && !s_axil_bvalid_reg;
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assign s_axil_wready = !s_axil_wvalid_reg && !s_axil_bvalid_reg;
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assign s_axil_bresp = s_axil_bresp_reg;
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assign s_axil_bvalid = s_axil_bvalid_reg;
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assign m_axil_awaddr = m_axil_awaddr_reg;
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assign m_axil_awprot = m_axil_awprot_reg;
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assign m_axil_awvalid = m_axil_awvalid_reg;
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assign m_axil_wdata = m_axil_wdata_reg;
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assign m_axil_wstrb = m_axil_wstrb_reg;
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assign m_axil_wvalid = m_axil_wvalid_reg;
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assign m_axil_bready = !m_axil_bvalid_reg;
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// slave side
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always @(posedge s_clk) begin
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s_axil_bvalid_reg <= s_axil_bvalid_reg && !s_axil_bready;
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if (!s_axil_awvalid_reg && !s_axil_bvalid_reg) begin
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s_axil_awaddr_reg <= s_axil_awaddr;
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s_axil_awprot_reg <= s_axil_awprot;
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s_axil_awvalid_reg <= s_axil_awvalid;
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end
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if (!s_axil_wvalid_reg && !s_axil_bvalid_reg) begin
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s_axil_wdata_reg <= s_axil_wdata;
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s_axil_wstrb_reg <= s_axil_wstrb;
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s_axil_wvalid_reg <= s_axil_wvalid;
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end
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case (s_state_reg)
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2'd0: begin
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if (s_axil_awvalid_reg && s_axil_wvalid_reg) begin
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s_state_reg <= 2'd1;
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s_flag_reg <= 1'b1;
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end
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end
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2'd1: begin
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if (m_flag_sync_reg_2) begin
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s_state_reg <= 2'd2;
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s_flag_reg <= 1'b0;
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s_axil_bresp_reg <= m_axil_bresp_reg;
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s_axil_bvalid_reg <= 1'b1;
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end
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end
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2'd2: begin
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if (!m_flag_sync_reg_2) begin
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s_state_reg <= 2'd0;
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s_axil_awvalid_reg <= 1'b0;
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s_axil_wvalid_reg <= 1'b0;
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end
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end
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endcase
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if (s_rst) begin
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s_state_reg <= 2'd0;
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s_flag_reg <= 1'b0;
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s_axil_awvalid_reg <= 1'b0;
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s_axil_wvalid_reg <= 1'b0;
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s_axil_bvalid_reg <= 1'b0;
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end
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end
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// synchronization
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always @(posedge s_clk) begin
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m_flag_sync_reg_1 <= m_flag_reg;
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m_flag_sync_reg_2 <= m_flag_sync_reg_1;
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end
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always @(posedge m_clk) begin
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s_flag_sync_reg_1 <= s_flag_reg;
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s_flag_sync_reg_2 <= s_flag_sync_reg_1;
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end
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// master side
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always @(posedge m_clk) begin
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m_axil_awvalid_reg <= m_axil_awvalid_reg && !m_axil_awready;
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m_axil_wvalid_reg <= m_axil_wvalid_reg && !m_axil_wready;
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if (!m_axil_bvalid_reg) begin
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m_axil_bresp_reg <= m_axil_bresp;
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m_axil_bvalid_reg <= m_axil_bvalid;
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end
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case (m_state_reg)
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2'd0: begin
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if (s_flag_sync_reg_2) begin
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m_state_reg <= 2'd1;
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m_axil_awaddr_reg <= s_axil_awaddr_reg;
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m_axil_awprot_reg <= s_axil_awprot_reg;
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m_axil_awvalid_reg <= 1'b1;
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m_axil_wdata_reg <= s_axil_wdata_reg;
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m_axil_wstrb_reg <= s_axil_wstrb_reg;
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m_axil_wvalid_reg <= 1'b1;
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m_axil_bvalid_reg <= 1'b0;
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end
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end
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2'd1: begin
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if (m_axil_bvalid_reg) begin
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m_flag_reg <= 1'b1;
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m_state_reg <= 2'd2;
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end
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end
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2'd2: begin
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if (!s_flag_sync_reg_2) begin
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m_state_reg <= 2'd0;
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m_flag_reg <= 1'b0;
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end
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end
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endcase
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if (m_rst) begin
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m_state_reg <= 2'd0;
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m_flag_reg <= 1'b0;
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m_axil_awvalid_reg <= 1'b0;
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m_axil_wvalid_reg <= 1'b0;
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m_axil_bvalid_reg <= 1'b1;
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end
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end
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endmodule
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