Alex Forencich 6c6648f114 fpga/mqnic: Add RAM inference directive to Intel designs ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2022-08-05 16:27:29 -07:00

..

app

fpga/mqnic: Clean up PCIe DMA IF flow control connections

2022-08-03 23:04:05 -07:00

common

fpga/common: add missing parameter

2022-08-03 23:04:23 -07:00

lib

merged changes in pcie

2022-08-05 16:25:42 -07:00

mqnic

fpga/mqnic: Add RAM inference directive to Intel designs

2022-08-05 16:27:29 -07:00

build_images_project.ini

Rework build_images settings

2022-07-13 01:18:42 -07:00

build_images.py

fpga/build_images.py: update quartus message parsing

2022-08-04 13:40:34 -07:00

collect_utilization.py

Add build automation scripts

2022-03-02 23:20:59 -08:00

watch.sh

Change interval

2022-07-13 01:18:55 -07:00