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404 lines
16 KiB
Verilog
404 lines
16 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Xilinx UltraScale PCIe interface adapter (Completer reQuest)
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*/
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module pcie_us_if_cq #
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(
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// Width of PCIe AXI stream interfaces in bits
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parameter AXIS_PCIE_DATA_WIDTH = 256,
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// PCIe AXI stream tkeep signal width (words per cycle)
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parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
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// PCIe AXI stream CQ tuser signal width
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parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
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// TLP data width
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parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
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// TLP strobe width
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parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input (CQ)
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*/
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input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
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input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
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input wire s_axis_cq_tvalid,
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output wire s_axis_cq_tready,
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input wire s_axis_cq_tlast,
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input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
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/*
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* TLP output (request to BAR)
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*/
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output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
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output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
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output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
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output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
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input wire rx_req_tlp_ready
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);
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parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
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parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
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parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
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// bus width assertions
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initial begin
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if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256 && AXIS_PCIE_DATA_WIDTH != 512) begin
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$error("Error: PCIe interface width must be 64, 128, 256, or 512 (instance %m)");
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$finish;
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end
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if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
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$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
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$finish;
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end
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if (AXIS_PCIE_DATA_WIDTH == 512) begin
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if (AXIS_PCIE_CQ_USER_WIDTH != 183) begin
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$error("Error: PCIe CQ tuser width must be 183 (instance %m)");
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$finish;
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end
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end else begin
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if (AXIS_PCIE_CQ_USER_WIDTH != 85 && AXIS_PCIE_CQ_USER_WIDTH != 88) begin
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$error("Error: PCIe CQ tuser width must be 85 or 88 (instance %m)");
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$finish;
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end
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end
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if (TLP_SEG_COUNT != 1) begin
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$error("Error: TLP segment count must be 1 (instance %m)");
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$finish;
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end
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if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
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$error("Error: Interface widths must match (instance %m)");
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$finish;
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end
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if (TLP_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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end
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localparam [2:0]
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TLP_FMT_3DW = 3'b000,
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TLP_FMT_4DW = 3'b001,
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TLP_FMT_3DW_DATA = 3'b010,
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TLP_FMT_4DW_DATA = 3'b011,
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TLP_FMT_PREFIX = 3'b100;
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localparam [3:0]
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REQ_MEM_READ = 4'b0000,
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REQ_MEM_WRITE = 4'b0001,
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REQ_IO_READ = 4'b0010,
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REQ_IO_WRITE = 4'b0011,
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REQ_MEM_FETCH_ADD = 4'b0100,
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REQ_MEM_SWAP = 4'b0101,
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REQ_MEM_CAS = 4'b0110,
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REQ_MEM_READ_LOCKED = 4'b0111,
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REQ_CFG_READ_0 = 4'b1000,
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REQ_CFG_READ_1 = 4'b1001,
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REQ_CFG_WRITE_0 = 4'b1010,
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REQ_CFG_WRITE_1 = 4'b1011,
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REQ_MSG = 4'b1100,
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REQ_MSG_VENDOR = 4'b1101,
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REQ_MSG_ATS = 4'b1110;
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reg [TLP_DATA_WIDTH-1:0] rx_req_tlp_data_reg = 0, rx_req_tlp_data_next;
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reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr_reg = 0, rx_req_tlp_hdr_next;
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reg [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id_reg = 0, rx_req_tlp_bar_id_next;
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reg [TLP_SEG_COUNT*7-1:0] rx_req_tlp_func_num_reg = 0, rx_req_tlp_func_num_next;
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reg [TLP_SEG_COUNT-1:0] rx_req_tlp_valid_reg = 0, rx_req_tlp_valid_next;
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reg [TLP_SEG_COUNT-1:0] rx_req_tlp_sop_reg = 0, rx_req_tlp_sop_next;
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reg [TLP_SEG_COUNT-1:0] rx_req_tlp_eop_reg = 0, rx_req_tlp_eop_next;
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assign rx_req_tlp_data = rx_req_tlp_data_reg;
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assign rx_req_tlp_hdr = rx_req_tlp_hdr_reg;
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assign rx_req_tlp_bar_id = rx_req_tlp_bar_id_reg;
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assign rx_req_tlp_func_num = rx_req_tlp_func_num_reg;
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assign rx_req_tlp_valid = rx_req_tlp_valid_reg;
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assign rx_req_tlp_sop = rx_req_tlp_sop_reg;
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assign rx_req_tlp_eop = rx_req_tlp_eop_reg;
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localparam [1:0]
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TLP_INPUT_STATE_IDLE = 2'd0,
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TLP_INPUT_STATE_HEADER = 2'd1,
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TLP_INPUT_STATE_PAYLOAD = 2'd2;
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reg [1:0] tlp_input_state_reg = TLP_INPUT_STATE_IDLE, tlp_input_state_next;
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reg s_axis_cq_tready_cmb;
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reg tlp_input_frame_reg = 1'b0, tlp_input_frame_next;
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reg [AXIS_PCIE_DATA_WIDTH-1:0] cq_tdata_int_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}, cq_tdata_int_next;
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reg cq_tvalid_int_reg = 1'b0, cq_tvalid_int_next;
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reg cq_tlast_int_reg = 1'b0, cq_tlast_int_next;
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reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] cq_tuser_int_reg = {AXIS_PCIE_CQ_USER_WIDTH{1'b0}}, cq_tuser_int_next;
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wire [AXIS_PCIE_DATA_WIDTH*2-1:0] cq_tdata = {s_axis_cq_tdata, cq_tdata_int_reg};
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assign s_axis_cq_tready = s_axis_cq_tready_cmb;
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always @* begin
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tlp_input_state_next = TLP_INPUT_STATE_IDLE;
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rx_req_tlp_data_next = rx_req_tlp_data_reg;
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rx_req_tlp_hdr_next = rx_req_tlp_hdr_reg;
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rx_req_tlp_bar_id_next = rx_req_tlp_bar_id_reg;
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rx_req_tlp_func_num_next = rx_req_tlp_func_num_reg;
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rx_req_tlp_valid_next = rx_req_tlp_valid_reg && !rx_req_tlp_ready;
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rx_req_tlp_sop_next = rx_req_tlp_sop_reg;
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rx_req_tlp_eop_next = rx_req_tlp_eop_reg;
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s_axis_cq_tready_cmb = rx_req_tlp_ready;
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tlp_input_frame_next = tlp_input_frame_reg;
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cq_tdata_int_next = cq_tdata_int_reg;
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cq_tvalid_int_next = cq_tvalid_int_reg;
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cq_tlast_int_next = cq_tlast_int_reg;
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cq_tuser_int_next = cq_tuser_int_reg;
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case (tlp_input_state_reg)
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TLP_INPUT_STATE_IDLE: begin
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s_axis_cq_tready_cmb = rx_req_tlp_ready;
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if (cq_tvalid_int_reg && rx_req_tlp_ready) begin
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// DW 0
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case (cq_tdata[78:75])
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REQ_MEM_READ: begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW; // fmt
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rx_req_tlp_hdr_next[124:120] = {5'b00000}; // type
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end
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REQ_MEM_WRITE: begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW_DATA; // fmt
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rx_req_tlp_hdr_next[124:120] = {5'b00000}; // type
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end
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REQ_IO_READ: begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW; // fmt
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rx_req_tlp_hdr_next[124:120] = {5'b00010}; // type
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end
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REQ_IO_WRITE: begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW_DATA; // fmt
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rx_req_tlp_hdr_next[124:120] = {5'b00010}; // type
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end
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REQ_MEM_FETCH_ADD: begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW_DATA; // fmt
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rx_req_tlp_hdr_next[124:120] = {5'b01100}; // type
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end
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REQ_MEM_SWAP: begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW_DATA; // fmt
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rx_req_tlp_hdr_next[124:120] = {5'b01101}; // type
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end
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REQ_MEM_CAS: begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW_DATA; // fmt
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rx_req_tlp_hdr_next[124:120] = {5'b01110}; // type
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end
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REQ_MEM_READ_LOCKED: begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW; // fmt
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rx_req_tlp_hdr_next[124:120] = {5'b00001}; // type
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end
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REQ_MSG: begin
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if (cq_tdata[74:64]) begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW_DATA; // fmt
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end else begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW; // fmt
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end
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rx_req_tlp_hdr_next[124:120] = {2'b10, cq_tdata[114:112]}; // type
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end
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REQ_MSG_VENDOR: begin
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if (cq_tdata[74:64]) begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW_DATA; // fmt
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end else begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW; // fmt
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end
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rx_req_tlp_hdr_next[124:120] = {2'b10, cq_tdata[114:112]}; // type
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end
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REQ_MSG_ATS: begin
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if (cq_tdata[74:64]) begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW_DATA; // fmt
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end else begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW; // fmt
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end
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rx_req_tlp_hdr_next[124:120] = {2'b10, cq_tdata[114:112]}; // type
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end
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default: begin
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rx_req_tlp_hdr_next[127:125] = TLP_FMT_4DW; // fmt
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rx_req_tlp_hdr_next[124:120] = {5'b00000}; // type
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end
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endcase
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rx_req_tlp_hdr_next[119] = 1'b0; // T9
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rx_req_tlp_hdr_next[118:116] = cq_tdata[123:121]; // TC
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rx_req_tlp_hdr_next[115] = 1'b0; // T8
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rx_req_tlp_hdr_next[114] = cq_tdata[126]; // attr
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rx_req_tlp_hdr_next[113] = 1'b0; // LN
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rx_req_tlp_hdr_next[112] = 1'b0; // TH
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rx_req_tlp_hdr_next[111] = 1'b0; // TD
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rx_req_tlp_hdr_next[110] = 1'b0; // EP
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rx_req_tlp_hdr_next[109:108] = cq_tdata[125:124]; // attr
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rx_req_tlp_hdr_next[107:106] = cq_tdata[1:0]; // AT
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rx_req_tlp_hdr_next[105:96] = cq_tdata[74:64]; // length
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// DW 1
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rx_req_tlp_hdr_next[95:80] = cq_tdata[95:80]; // requester ID
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rx_req_tlp_hdr_next[79:72] = cq_tdata[103:96]; // tag
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if (AXIS_PCIE_DATA_WIDTH == 512) begin
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rx_req_tlp_hdr_next[71:68] = cq_tuser_int_reg[11:8]; // last BE
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rx_req_tlp_hdr_next[67:64] = cq_tuser_int_reg[3:0]; // first BE
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end else begin
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rx_req_tlp_hdr_next[71:68] = cq_tuser_int_reg[7:4]; // last BE
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rx_req_tlp_hdr_next[67:64] = cq_tuser_int_reg[3:0]; // first BE
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end
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// DW 2+3
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rx_req_tlp_hdr_next[63:2] = cq_tdata[63:2]; // address
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rx_req_tlp_hdr_next[1:0] = 2'b00; // PH
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rx_req_tlp_bar_id_next = cq_tdata[114:112];
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rx_req_tlp_func_num_next = cq_tdata[111:104];
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if (AXIS_PCIE_DATA_WIDTH > 64) begin
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rx_req_tlp_data_next = cq_tdata[AXIS_PCIE_DATA_WIDTH+128-1:128];
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rx_req_tlp_sop_next = 1'b1;
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rx_req_tlp_eop_next = 1'b0;
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tlp_input_frame_next = 1'b1;
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if (cq_tlast_int_reg) begin
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rx_req_tlp_valid_next = 1'b1;
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rx_req_tlp_eop_next = 1'b1;
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cq_tvalid_int_next = 1'b0;
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tlp_input_frame_next = 1'b0;
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tlp_input_state_next = TLP_INPUT_STATE_IDLE;
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end else if (s_axis_cq_tready && s_axis_cq_tvalid) begin
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rx_req_tlp_valid_next = 1'b1;
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tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
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end else begin
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tlp_input_state_next = TLP_INPUT_STATE_IDLE;
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end
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end else begin
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if (cq_tlast_int_reg) begin
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cq_tvalid_int_next = 1'b0;
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tlp_input_frame_next = 1'b0;
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tlp_input_state_next = TLP_INPUT_STATE_IDLE;
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end else if (s_axis_cq_tready && s_axis_cq_tvalid) begin
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tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
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end else begin
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tlp_input_state_next = TLP_INPUT_STATE_IDLE;
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end
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end
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end else begin
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tlp_input_state_next = TLP_INPUT_STATE_IDLE;
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end
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end
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TLP_INPUT_STATE_PAYLOAD: begin
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s_axis_cq_tready_cmb = rx_req_tlp_ready;
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if (cq_tvalid_int_reg && rx_req_tlp_ready) begin
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if (AXIS_PCIE_DATA_WIDTH > 128) begin
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rx_req_tlp_data_next = cq_tdata[AXIS_PCIE_DATA_WIDTH+128-1:128];
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rx_req_tlp_sop_next = 1'b0;
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end else begin
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rx_req_tlp_data_next = s_axis_cq_tdata;
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rx_req_tlp_sop_next = !tlp_input_frame_reg;
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end
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rx_req_tlp_eop_next = 1'b0;
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if (cq_tlast_int_reg) begin
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rx_req_tlp_valid_next = 1'b1;
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rx_req_tlp_eop_next = 1'b1;
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cq_tvalid_int_next = 1'b0;
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tlp_input_frame_next = 1'b0;
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tlp_input_state_next = TLP_INPUT_STATE_IDLE;
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end else if (s_axis_cq_tready && s_axis_cq_tvalid) begin
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rx_req_tlp_valid_next = 1'b1;
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tlp_input_frame_next = 1'b1;
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tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
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end else begin
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tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
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end
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end else begin
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tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
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end
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end
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endcase
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if (s_axis_cq_tready && s_axis_cq_tvalid) begin
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cq_tdata_int_next = s_axis_cq_tdata;
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cq_tvalid_int_next = s_axis_cq_tvalid;
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cq_tlast_int_next = s_axis_cq_tlast;
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cq_tuser_int_next = s_axis_cq_tuser;
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end
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end
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always @(posedge clk) begin
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tlp_input_state_reg <= tlp_input_state_next;
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rx_req_tlp_data_reg <= rx_req_tlp_data_next;
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rx_req_tlp_hdr_reg <= rx_req_tlp_hdr_next;
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rx_req_tlp_bar_id_reg <= rx_req_tlp_bar_id_next;
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rx_req_tlp_func_num_reg <= rx_req_tlp_func_num_next;
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rx_req_tlp_valid_reg <= rx_req_tlp_valid_next;
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rx_req_tlp_sop_reg <= rx_req_tlp_sop_next;
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rx_req_tlp_eop_reg <= rx_req_tlp_eop_next;
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|
|
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tlp_input_frame_reg <= tlp_input_frame_next;
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|
|
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cq_tdata_int_reg <= cq_tdata_int_next;
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|
cq_tvalid_int_reg <= cq_tvalid_int_next;
|
|
cq_tlast_int_reg <= cq_tlast_int_next;
|
|
cq_tuser_int_reg <= cq_tuser_int_next;
|
|
|
|
if (rst) begin
|
|
tlp_input_state_reg <= TLP_INPUT_STATE_IDLE;
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|
|
|
rx_req_tlp_valid_reg <= 0;
|
|
|
|
cq_tvalid_int_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
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endmodule
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|
|
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`resetall
|