Alex Forencich a25c4b17eb Add AXI shared interconnect and testbench

2018-08-22 23:42:31 -07:00

..

axi.py

Change default awcache/arcache value

2018-08-17 16:29:12 -07:00

axil.py

Don't crash when omitting read or write port connections

2018-08-16 12:50:14 -07:00

test_axi_adapter_16_32.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_adapter_16_32.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_adapter_32_16.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_adapter_32_16.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_adapter_32_32.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_adapter_32_32.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_fifo_delay.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_fifo_delay.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_fifo.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_fifo.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_interconnect_4x4.py

Add AXI shared interconnect and testbench

2018-08-22 23:42:31 -07:00

test_axi_interconnect_4x4.v

Add AXI shared interconnect and testbench

2018-08-22 23:42:31 -07:00

test_axi_ram.py

Don't use narrow bursts for setup and checking in AXI RAM testbench

2018-08-14 23:44:15 -07:00

test_axi_ram.v

Initial commit

2018-07-29 19:04:30 -07:00

test_axi_register.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi_register.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axi.py

Properly handle read bursts in AXI model

2018-08-13 15:12:56 -07:00

test_axil_adapter_16_32.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axil_adapter_16_32.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axil_adapter_32_16.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axil_adapter_32_16.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axil_adapter_32_32.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axil_adapter_32_32.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axil_interconnect_4x4.py

Add decode error tests

2018-08-22 20:43:28 -07:00

test_axil_interconnect_4x4.v

Add AXI lite shared interconnect module and testbench

2018-08-22 20:34:31 -07:00

test_axil_ram.py

Add AXI lite RAM module and testbench

2018-08-14 23:49:40 -07:00

test_axil_ram.v

Add AXI lite RAM module and testbench

2018-08-14 23:49:40 -07:00

test_axil_register.py

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axil_register.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

test_axil.py

Add MyHDL AXI4 Lite master model, RAM model, and testbench

2018-08-14 23:49:11 -07:00