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552 lines
18 KiB
Verilog
552 lines
18 KiB
Verilog
/*
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Copyright (c) 2022 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PCIe MSI-X module
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*/
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module pcie_msix #
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(
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// Interrupt configuration
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parameter IRQ_INDEX_WIDTH = 11,
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// AXI-lite interface configuration
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parameter AXIL_DATA_WIDTH = 32,
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parameter AXIL_ADDR_WIDTH = IRQ_INDEX_WIDTH+5,
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
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// TLP interface configuration
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parameter TLP_HDR_WIDTH = 128,
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parameter TLP_FORCE_64_BIT_ADDR = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI lite interface for MSI-X tables
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*/
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
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input wire [2:0] s_axil_awprot,
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input wire s_axil_awvalid,
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output wire s_axil_awready,
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input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
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input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
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input wire s_axil_wvalid,
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output wire s_axil_wready,
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output wire [1:0] s_axil_bresp,
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output wire s_axil_bvalid,
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input wire s_axil_bready,
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
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input wire [2:0] s_axil_arprot,
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input wire s_axil_arvalid,
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output wire s_axil_arready,
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output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
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output wire [1:0] s_axil_rresp,
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output wire s_axil_rvalid,
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input wire s_axil_rready,
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/*
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* Interrupt request input
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*/
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input wire [IRQ_INDEX_WIDTH-1:0] irq_index,
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input wire irq_valid,
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output wire irq_ready,
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/*
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* Memory write TLP output
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*/
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output wire [31:0] tx_wr_req_tlp_data,
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output wire tx_wr_req_tlp_strb,
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output wire [TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
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output wire tx_wr_req_tlp_valid,
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output wire tx_wr_req_tlp_sop,
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output wire tx_wr_req_tlp_eop,
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input wire tx_wr_req_tlp_ready,
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/*
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* Configuration
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*/
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input wire [15:0] requester_id,
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input wire msix_enable,
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input wire msix_mask
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);
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parameter TBL_ADDR_WIDTH = IRQ_INDEX_WIDTH+1;
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parameter PBA_ADDR_WIDTH = IRQ_INDEX_WIDTH > 6 ? IRQ_INDEX_WIDTH-6 : 0;
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parameter PBA_ADDR_WIDTH_INT = PBA_ADDR_WIDTH > 0 ? PBA_ADDR_WIDTH : 1;
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parameter INDEX_SHIFT = $clog2(64/8);
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parameter WORD_SELECT_SHIFT = $clog2(AXIL_DATA_WIDTH/8);
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parameter WORD_SELECT_WIDTH = 64 > AXIL_DATA_WIDTH ? $clog2((64+7)/8) - $clog2(AXIL_DATA_WIDTH/8) : 0;
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// bus width assertions
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initial begin
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if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
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$error("Error: AXI lite interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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if (AXIL_DATA_WIDTH > 64) begin
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$error("Error: AXI lite data width must be 64 or less (instance %m)");
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$finish;
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end
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if (AXIL_ADDR_WIDTH < IRQ_INDEX_WIDTH+5) begin
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$error("Error: AXI lite address width too narrow (instance %m)");
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$finish;
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end
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if (IRQ_INDEX_WIDTH > 11) begin
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$error("Error: IRQ index width must be 11 or less (instance %m)");
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$finish;
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end
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end
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localparam [2:0]
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TLP_FMT_3DW = 3'b000,
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TLP_FMT_4DW = 3'b001,
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TLP_FMT_3DW_DATA = 3'b010,
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TLP_FMT_4DW_DATA = 3'b011,
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TLP_FMT_PREFIX = 3'b100;
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_READ_TBL_1 = 2'd1,
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STATE_READ_TBL_2 = 2'd2,
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STATE_SEND_TLP = 2'd3;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg [IRQ_INDEX_WIDTH-1:0] irq_index_reg = 0, irq_index_next;
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reg [63:0] vec_addr_reg = 0, vec_addr_next;
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reg [31:0] vec_data_reg = 0, vec_data_next;
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reg vec_mask_reg = 1'b0, vec_mask_next;
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reg last_read_reg = 1'b0, last_read_next;
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reg [127:0] tlp_hdr;
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reg read_eligible;
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reg write_eligible;
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reg tbl_axil_mem_rd_en;
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reg tbl_axil_mem_wr_en;
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reg [7:0] tbl_axil_mem_wr_be;
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reg [63:0] tbl_axil_mem_wr_data;
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reg pba_axil_mem_rd_en;
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reg tbl_mem_rd_en;
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reg tbl_mem_wr_en;
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reg [TBL_ADDR_WIDTH-1:0] tbl_mem_addr;
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reg [63:0] tbl_mem_wr_data;
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reg pba_mem_rd_en;
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reg pba_mem_wr_en;
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reg [PBA_ADDR_WIDTH-1:0] pba_mem_addr;
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reg [63:0] pba_mem_wr_data;
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reg s_axil_awready_reg = 1'b0, s_axil_awready_next;
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reg s_axil_wready_reg = 1'b0, s_axil_wready_next;
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reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
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reg s_axil_arready_reg = 1'b0, s_axil_arready_next;
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reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}, s_axil_rdata_next;
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reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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reg irq_ready_reg = 1'b0, irq_ready_next;
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reg [31:0] tx_wr_req_tlp_data_reg = 0, tx_wr_req_tlp_data_next;
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reg [TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr_reg = 0, tx_wr_req_tlp_hdr_next;
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reg tx_wr_req_tlp_valid_reg = 0, tx_wr_req_tlp_valid_next;
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// MSI-X table
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(* ramstyle = "no_rw_check, mlab" *)
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reg [63:0] tbl_mem[(2**TBL_ADDR_WIDTH)-1:0];
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// MSI-X PBA
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [63:0] pba_mem[(2**PBA_ADDR_WIDTH)-1:0];
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reg tbl_rd_data_valid_reg = 1'b0, tbl_rd_data_valid_next;
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reg pba_rd_data_valid_reg = 1'b0, pba_rd_data_valid_next;
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reg [WORD_SELECT_WIDTH-1:0] rd_data_shift_reg = 0, rd_data_shift_next;
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reg [63:0] tbl_mem_rd_data_reg = 0;
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reg [63:0] pba_mem_rd_data_reg = 0;
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reg [63:0] tbl_axil_mem_rd_data_reg = 0;
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reg [63:0] pba_axil_mem_rd_data_reg = 0;
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wire [TBL_ADDR_WIDTH-1:0] s_axil_awaddr_index = s_axil_awaddr >> INDEX_SHIFT;
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wire [WORD_SELECT_WIDTH-1:0] s_axil_awaddr_word = AXIL_DATA_WIDTH < 64 ? s_axil_awaddr >> WORD_SELECT_SHIFT : 0;
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wire [TBL_ADDR_WIDTH-1:0] s_axil_araddr_index = s_axil_araddr >> INDEX_SHIFT;
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wire [WORD_SELECT_WIDTH-1:0] s_axil_araddr_word = AXIL_DATA_WIDTH < 64 ? s_axil_araddr >> WORD_SELECT_SHIFT : 0;
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assign s_axil_awready = s_axil_awready_reg;
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assign s_axil_wready = s_axil_wready_reg;
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assign s_axil_bresp = 2'b00;
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assign s_axil_bvalid = s_axil_bvalid_reg;
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assign s_axil_arready = s_axil_arready_reg;
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assign s_axil_rdata = s_axil_rdata_reg;
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assign s_axil_rresp = 2'b00;
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assign s_axil_rvalid = s_axil_rvalid_reg;
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assign irq_ready = irq_ready_reg;
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assign tx_wr_req_tlp_data = tx_wr_req_tlp_data_reg;
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assign tx_wr_req_tlp_strb = 1;
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assign tx_wr_req_tlp_hdr = tx_wr_req_tlp_hdr_reg;
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assign tx_wr_req_tlp_valid = tx_wr_req_tlp_valid_reg;
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assign tx_wr_req_tlp_sop = 1'b1;
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assign tx_wr_req_tlp_eop = 1'b1;
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integer i;
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initial begin
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for (i = 0; i < 2**TBL_ADDR_WIDTH; i = i + 1) begin
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tbl_mem[i] = 0;
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end
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for (i = 0; i < 2**PBA_ADDR_WIDTH; i = i + 1) begin
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pba_mem[i] = 0;
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end
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end
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always @* begin
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state_next = STATE_IDLE;
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tbl_mem_rd_en = 1'b0;
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tbl_mem_wr_en = 1'b0;
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tbl_mem_addr = {irq_index_reg, 1'b0};
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tbl_mem_wr_data = 0;
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pba_mem_rd_en = 1'b0;
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pba_mem_wr_en = 1'b0;
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pba_mem_addr = irq_index_reg >> 5;
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pba_mem_wr_data = 0;
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irq_index_next = irq_index_reg;
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vec_addr_next = vec_addr_reg;
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vec_data_next = vec_data_reg;
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vec_mask_next = vec_mask_reg;
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irq_ready_next = 1'b0;
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tx_wr_req_tlp_data_next = tx_wr_req_tlp_data_reg;
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tx_wr_req_tlp_hdr_next = tx_wr_req_tlp_hdr_reg;
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tx_wr_req_tlp_valid_next = tx_wr_req_tlp_valid_reg && !tx_wr_req_tlp_ready;
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// TLP header
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// DW 0
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if (((vec_addr_reg[63:2] >> 30) != 0) || TLP_FORCE_64_BIT_ADDR) begin
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tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt - 4DW with data
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end else begin
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tlp_hdr[127:125] = TLP_FMT_3DW_DATA; // fmt - 3DW with data
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end
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tlp_hdr[124:120] = 5'b00000; // type - write
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tlp_hdr[119] = 1'b0; // T9
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tlp_hdr[118:116] = 3'b000; // TC
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tlp_hdr[115] = 1'b0; // T8
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tlp_hdr[114] = 1'b0; // attr
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tlp_hdr[113] = 1'b0; // LN
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tlp_hdr[112] = 1'b0; // TH
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tlp_hdr[111] = 1'b0; // TD
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tlp_hdr[110] = 1'b0; // EP
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tlp_hdr[109:108] = 2'b00; // attr
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tlp_hdr[107:106] = 3'b000; // AT
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tlp_hdr[105:96] = 10'd1; // length
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// DW 1
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tlp_hdr[95:80] = requester_id; // requester ID
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tlp_hdr[79:72] = 8'd0; // tag
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tlp_hdr[71:68] = 4'b0000; // last BE
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tlp_hdr[67:64] = 4'b1111; // first BE
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if (((vec_addr_reg[63:2] >> 30) != 0) || TLP_FORCE_64_BIT_ADDR) begin
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// DW 2+3
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tlp_hdr[63:2] = vec_addr_reg[63:2]; // address
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tlp_hdr[1:0] = 2'b00; // PH
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end else begin
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// DW 2
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tlp_hdr[63:34] = vec_addr_reg[63:2]; // address
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tlp_hdr[33:32] = 2'b00; // PH
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// DW 3
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tlp_hdr[31:0] = 32'd0;
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end
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case (state_reg)
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STATE_IDLE: begin
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irq_ready_next = 1'b1;
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if (irq_valid && irq_ready) begin
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// new request
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irq_ready_next = 1'b0;
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irq_index_next = irq_index;
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tbl_mem_rd_en = 1'b1;
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tbl_mem_addr = {irq_index_next, 1'b0};
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pba_mem_rd_en = 1'b1;
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pba_mem_addr = irq_index_next >> 6;
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state_next = STATE_READ_TBL_1;
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end else if (!irq_valid && msix_enable && !msix_mask) begin
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// no new request waiting, scan PBA for masked requests
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if (pba_mem_rd_data_reg[irq_index_reg & 6'h3f]) begin
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// PBA bit for current index is set, try issuing it
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irq_ready_next = 1'b0;
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tbl_mem_rd_en = 1'b1;
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tbl_mem_addr = {irq_index_next, 1'b0};
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pba_mem_rd_en = 1'b1;
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pba_mem_addr = irq_index_next >> 6;
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state_next = STATE_READ_TBL_1;
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end else begin
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// PBA bit for current index is not set
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if (pba_mem_rd_data_reg) begin
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// at least one bit set in current group, move to next index
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irq_index_next = irq_index_reg + 1;
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end else begin
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// no bits set in current group, move to next group
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irq_index_next = (irq_index_reg & ({IRQ_INDEX_WIDTH{1'b1}} << 6)) + 7'd64;
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end
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pba_mem_rd_en = 1'b1;
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pba_mem_addr = irq_index_next >> 6;
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_READ_TBL_1: begin
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// handle first table read
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tbl_mem_rd_en = 1'b1;
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tbl_mem_addr = {irq_index_reg, 1'b1};
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vec_addr_next = {tbl_mem_rd_data_reg[63:2], 2'b00};
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state_next = STATE_READ_TBL_2;
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end
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STATE_READ_TBL_2: begin
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// handle second table read
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vec_data_next = tbl_mem_rd_data_reg[31:0];
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vec_mask_next = tbl_mem_rd_data_reg[32];
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if (msix_enable && !msix_mask && !vec_mask_next) begin
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// send TLP
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state_next = STATE_SEND_TLP;
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end else begin
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// set PBA bit
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pba_mem_wr_en = 1'b1;
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pba_mem_wr_data = pba_mem_rd_data_reg | (1 << (irq_index_reg & 6'h3F));
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irq_ready_next = 1'b1;
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state_next = STATE_IDLE;
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end
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end
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STATE_SEND_TLP: begin
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if (!tx_wr_req_tlp_valid || tx_wr_req_tlp_ready) begin
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// send TLP
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tx_wr_req_tlp_data_next = vec_data_reg;
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tx_wr_req_tlp_hdr_next = tlp_hdr;
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tx_wr_req_tlp_valid_next = 1'b1;
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// clear PBA bit
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pba_mem_wr_en = 1'b1;
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pba_mem_wr_data = pba_mem_rd_data_reg & ~(1 << (irq_index_reg & 6'h3F));
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// increment index so we don't check the same PBA bit immediately
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irq_index_next = irq_index_reg + 1;
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irq_ready_next = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_SEND_TLP;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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state_reg <= state_next;
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irq_index_reg <= irq_index_next;
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vec_addr_reg <= vec_addr_next;
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vec_data_reg <= vec_data_next;
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vec_mask_reg <= vec_mask_next;
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irq_ready_reg <= irq_ready_next;
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tx_wr_req_tlp_data_reg <= tx_wr_req_tlp_data_next;
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tx_wr_req_tlp_hdr_reg <= tx_wr_req_tlp_hdr_next;
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tx_wr_req_tlp_valid_reg <= tx_wr_req_tlp_valid_next;
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if (tbl_mem_rd_en) begin
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tbl_mem_rd_data_reg <= tbl_mem[tbl_mem_addr];
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end else if (tbl_mem_wr_en) begin
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tbl_mem[tbl_mem_addr] <= tbl_mem_wr_data;
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end
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if (pba_mem_rd_en) begin
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pba_mem_rd_data_reg <= pba_mem[pba_mem_addr];
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end else if (pba_mem_wr_en) begin
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pba_mem[pba_mem_addr] <= pba_mem_wr_data;
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end
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if (rst) begin
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state_reg <= STATE_IDLE;
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irq_ready_reg <= 1'b0;
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tx_wr_req_tlp_valid_reg <= 1'b0;
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end
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end
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// AXI lite interface
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always @* begin
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tbl_axil_mem_rd_en = 1'b0;
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tbl_axil_mem_wr_en = 1'b0;
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tbl_axil_mem_wr_be = s_axil_wstrb << (s_axil_awaddr_word * AXIL_STRB_WIDTH);
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tbl_axil_mem_wr_data = {2**WORD_SELECT_WIDTH{s_axil_wdata}};
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pba_axil_mem_rd_en = 1'b0;
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tbl_rd_data_valid_next = tbl_rd_data_valid_reg;
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pba_rd_data_valid_next = pba_rd_data_valid_reg;
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rd_data_shift_next = rd_data_shift_reg;
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last_read_next = last_read_reg;
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s_axil_awready_next = 1'b0;
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s_axil_wready_next = 1'b0;
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s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
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s_axil_arready_next = 1'b0;
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s_axil_rdata_next = s_axil_rdata_reg;
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s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready;
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write_eligible = s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!s_axil_awready && !s_axil_wready);
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read_eligible = s_axil_arvalid && (!s_axil_rvalid || s_axil_rready || !(tbl_rd_data_valid_reg || pba_rd_data_valid_reg)) && (!s_axil_arready);
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if ((tbl_rd_data_valid_reg || pba_rd_data_valid_reg) && (!s_axil_rvalid || s_axil_rready)) begin
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s_axil_rvalid_next = 1'b1;
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tbl_rd_data_valid_next = 1'b0;
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pba_rd_data_valid_next = 1'b0;
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|
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if (tbl_rd_data_valid_reg) begin
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if (AXIL_DATA_WIDTH < 64) begin
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s_axil_rdata_next = tbl_axil_mem_rd_data_reg >> rd_data_shift_reg*AXIL_DATA_WIDTH;
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end else begin
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s_axil_rdata_next = tbl_axil_mem_rd_data_reg;
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end
|
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end else begin
|
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if (AXIL_DATA_WIDTH < 64) begin
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s_axil_rdata_next = pba_axil_mem_rd_data_reg >> rd_data_shift_reg*AXIL_DATA_WIDTH;
|
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end else begin
|
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s_axil_rdata_next = pba_axil_mem_rd_data_reg;
|
|
end
|
|
end
|
|
end
|
|
|
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if (write_eligible && (!read_eligible || last_read_reg)) begin
|
|
last_read_next = 1'b0;
|
|
|
|
s_axil_awready_next = 1'b1;
|
|
s_axil_wready_next = 1'b1;
|
|
s_axil_bvalid_next = 1'b1;
|
|
|
|
if (s_axil_awaddr[AXIL_ADDR_WIDTH-1] == 0) begin
|
|
tbl_axil_mem_wr_en = 1'b1;
|
|
end
|
|
end else if (read_eligible) begin
|
|
last_read_next = 1'b1;
|
|
|
|
s_axil_arready_next = 1'b1;
|
|
|
|
rd_data_shift_next = s_axil_araddr_word;
|
|
|
|
if (s_axil_araddr[AXIL_ADDR_WIDTH-1] == 0) begin
|
|
tbl_axil_mem_rd_en = 1'b1;
|
|
tbl_rd_data_valid_next = 1'b1;
|
|
end else begin
|
|
pba_axil_mem_rd_en = 1'b1;
|
|
pba_rd_data_valid_next = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
tbl_rd_data_valid_reg <= tbl_rd_data_valid_next;
|
|
pba_rd_data_valid_reg <= pba_rd_data_valid_next;
|
|
rd_data_shift_reg <= rd_data_shift_next;
|
|
|
|
last_read_reg <= last_read_next;
|
|
|
|
s_axil_awready_reg <= s_axil_awready_next;
|
|
s_axil_wready_reg <= s_axil_wready_next;
|
|
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
|
|
|
s_axil_arready_reg <= s_axil_arready_next;
|
|
s_axil_rdata_reg <= s_axil_rdata_next;
|
|
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
|
|
|
if (tbl_axil_mem_rd_en) begin
|
|
tbl_axil_mem_rd_data_reg <= tbl_mem[s_axil_araddr_index];
|
|
end else begin
|
|
for (i = 0; i < 8; i = i + 1) begin
|
|
if (tbl_axil_mem_wr_en && tbl_axil_mem_wr_be[i]) begin
|
|
tbl_mem[s_axil_awaddr_index][8*i +: 8] <= tbl_axil_mem_wr_data[8*i +: 8];
|
|
end
|
|
end
|
|
end
|
|
|
|
if (pba_axil_mem_rd_en) begin
|
|
pba_axil_mem_rd_data_reg <= pba_mem[s_axil_araddr_index];
|
|
end
|
|
|
|
if (rst) begin
|
|
tbl_rd_data_valid_reg <= 1'b0;
|
|
pba_rd_data_valid_reg <= 1'b0;
|
|
last_read_reg <= 1'b0;
|
|
|
|
s_axil_awready_reg <= 1'b0;
|
|
s_axil_wready_reg <= 1'b0;
|
|
s_axil_bvalid_reg <= 1'b0;
|
|
|
|
s_axil_arready_reg <= 1'b0;
|
|
s_axil_rvalid_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|