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83 lines
4.2 KiB
Tcl
83 lines
4.2 KiB
Tcl
# Timing constraints for the Intel Stratix 10 DX FPGA development board
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set_time_format -unit ns -decimal_places 3
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# Clock constraints
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create_clock -period 7.519 -name {clk_133m_ddr4_1} [ get_ports {clk_133m_ddr4_1_p} ]
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create_clock -period 7.519 -name {clk_133m_ddr4_0} [ get_ports {clk_133m_ddr4_0_p} ]
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create_clock -period 7.519 -name {clk_133m_dimm_1} [ get_ports {clk_133m_dimm_1_p} ]
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create_clock -period 7.519 -name {clk_133m_dimm_0} [ get_ports {clk_133m_dimm_0_p} ]
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create_clock -period 10.000 -name {clk2_100m_fpga_2i} [ get_ports {clk2_100m_fpga_2i_p} ]
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create_clock -period 10.000 -name {clk2_100m_fpga_2j_0} [ get_ports {clk2_100m_fpga_2j_0_p} ]
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create_clock -period 10.000 -name {clk2_100m_fpga_2j_1} [ get_ports {clk2_100m_fpga_2j_1_p} ]
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create_clock -period 10.000 -name {clk_100m_fpga_3h} [ get_ports {clk_100m_fpga_3h_p} ]
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create_clock -period 10.000 -name {clk_100m_fpga_3l_0} [ get_ports {clk_100m_fpga_3l_0_p} ]
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create_clock -period 10.000 -name {clk_100m_fpga_3l_1} [ get_ports {clk_100m_fpga_3l_1_p} ]
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create_clock -period 20.000 -name {clk2_fpga_50m} [ get_ports {clk2_fpga_50m} ]
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create_clock -period 10.000 -name {clk_100m_pcie_0} [ get_ports {clk_100m_pcie_0_p} ]
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create_clock -period 10.000 -name {clk_100m_pcie_1} [ get_ports {clk_100m_pcie_1_p} ]
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create_clock -period 10.000 -name {clk_100m_upi0_0} [ get_ports {clk_100m_upi0_0_p} ]
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create_clock -period 10.000 -name {clk_100m_upi0_1} [ get_ports {clk_100m_upi0_1_p} ]
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create_clock -period 10.000 -name {clk_100m_upi1_0} [ get_ports {clk_100m_upi1_0_p} ]
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create_clock -period 10.000 -name {clk_100m_upi1_1} [ get_ports {clk_100m_upi1_1_p} ]
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create_clock -period 10.000 -name {clk_100m_upi2_0} [ get_ports {clk_100m_upi2_0_p} ]
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create_clock -period 10.000 -name {clk_100m_upi2_1} [ get_ports {clk_100m_upi2_1_p} ]
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create_clock -period 3.2 -name {clk_312p5m_qsfp0} [ get_ports {clk_312p5m_qsfp0_p} ]
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create_clock -period 6.4 -name {clk_156p25m_qsfp0} [ get_ports {clk_156p25m_qsfp0_p} ]
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create_clock -period 3.2 -name {clk_312p5m_qsfp1} [ get_ports {clk_312p5m_qsfp1_p} ]
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create_clock -period 6.4 -name {clk_156p25m_qsfp1} [ get_ports {clk_156p25m_qsfp1_p} ]
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create_clock -period 3.2 -name {clk_312p5m_qsfp2} [ get_ports {clk_312p5m_qsfp2_p} ]
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derive_clock_uncertainty
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set_clock_groups -asynchronous -group [ get_clocks {clk_133m_ddr4_1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_133m_ddr4_0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_133m_dimm_1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_133m_dimm_0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk2_100m_fpga_2i} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk2_100m_fpga_2j_0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk2_100m_fpga_2j_1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_fpga_3h} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_fpga_3l_0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_fpga_3l_1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk2_fpga_50m} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_pcie_0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_pcie_1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_upi0_0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_upi0_1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_upi1_0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_upi1_1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_upi2_0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_100m_upi2_1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_312p5m_qsfp0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_156p25m_qsfp0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_312p5m_qsfp1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_156p25m_qsfp1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_312p5m_qsfp2} ]
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# JTAG constraints
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create_clock -name {altera_reserved_tck} -period 40.800 {altera_reserved_tck}
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set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
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# IO constraints
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set_false_path -from "cpu_resetn"
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set_false_path -to "user_led_g[*]"
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set_false_path -from "pcie_rst_n"
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