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516 lines
17 KiB
Verilog
516 lines
17 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Intel Stratix 10 H-Tile/L-Tile PCIe interface adapter
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*/
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module pcie_s10_if #
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(
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// H-Tile/L-Tile AVST segment count
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parameter SEG_COUNT = 1,
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// H-Tile/L-Tile AVST segment data width
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parameter SEG_DATA_WIDTH = 256,
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// H-Tile/L-Tile AVST segment empty signal width
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parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
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// TLP data width
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parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH,
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// TLP strobe width
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parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// TX sequence number width
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parameter TX_SEQ_NUM_WIDTH = 6,
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// Tile selection (0 for H-Tile, 1 for L-Tile)
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parameter L_TILE = 0,
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// Number of PFs
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parameter PF_COUNT = 1,
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// Number of VFs
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parameter VF_COUNT = 0,
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// Total number of functions
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parameter F_COUNT = PF_COUNT+VF_COUNT,
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// IO bar index
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// rx_st_bar_range = 6 is mapped to IO_BAR_INDEX on rx_req_tlp_bar_id
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parameter IO_BAR_INDEX = 5,
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// enable MSI support
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parameter MSI_ENABLE = 1,
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// MSI vector count
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parameter MSI_COUNT = 32
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)
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(
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input wire clk,
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input wire rst,
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/*
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* H-Tile/L-Tile RX AVST interface
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*/
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input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
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input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
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input wire [SEG_COUNT-1:0] rx_st_sop,
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input wire [SEG_COUNT-1:0] rx_st_eop,
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input wire [SEG_COUNT-1:0] rx_st_valid,
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output wire rx_st_ready,
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input wire [SEG_COUNT-1:0] rx_st_vf_active,
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input wire [SEG_COUNT*2-1:0] rx_st_func_num,
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input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
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input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
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/*
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* H-Tile/L-Tile TX AVST interface
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*/
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output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
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output wire [SEG_COUNT-1:0] tx_st_sop,
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output wire [SEG_COUNT-1:0] tx_st_eop,
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output wire [SEG_COUNT-1:0] tx_st_valid,
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input wire tx_st_ready,
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output wire [SEG_COUNT-1:0] tx_st_err,
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/*
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* H-Tile/L-Tile TX flow control
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*/
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input wire [7:0] tx_ph_cdts,
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input wire [11:0] tx_pd_cdts,
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input wire [7:0] tx_nph_cdts,
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input wire [11:0] tx_npd_cdts,
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input wire [7:0] tx_cplh_cdts,
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input wire [11:0] tx_cpld_cdts,
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input wire [SEG_COUNT-1:0] tx_hdr_cdts_consumed,
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input wire [SEG_COUNT-1:0] tx_data_cdts_consumed,
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input wire [SEG_COUNT*2-1:0] tx_cdts_type,
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input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
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/*
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* H-Tile/L-Tile MSI interrupt interface
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*/
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output wire app_msi_req,
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input wire app_msi_ack,
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output wire [2:0] app_msi_tc,
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output wire [4:0] app_msi_num,
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output wire [1:0] app_msi_func_num,
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/*
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* H-Tile/L-Tile configuration interface
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*/
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input wire [31:0] tl_cfg_ctl,
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input wire [4:0] tl_cfg_add,
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input wire [1:0] tl_cfg_func,
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/*
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* TLP output (request to BAR)
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*/
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output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
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output wire [TLP_STRB_WIDTH-1:0] rx_req_tlp_strb,
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output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
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output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
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output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
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input wire rx_req_tlp_ready,
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/*
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* TLP output (completion to DMA)
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*/
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output wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
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output wire [TLP_STRB_WIDTH-1:0] rx_cpl_tlp_strb,
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output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
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output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
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output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
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output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
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output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
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input wire rx_cpl_tlp_ready,
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/*
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* TLP input (read request from DMA)
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*/
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
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input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
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output wire tx_rd_req_tlp_ready,
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/*
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* Transmit sequence number output (DMA read request)
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*/
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output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
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output wire [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
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/*
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* TLP input (write request from DMA)
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*/
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input wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
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input wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
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input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
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output wire tx_wr_req_tlp_ready,
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/*
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* Transmit sequence number output (DMA write request)
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*/
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output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
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output wire [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid,
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/*
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* TLP input (completion from BAR)
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*/
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input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
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input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
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output wire tx_cpl_tlp_ready,
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/*
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* TLP input (write request from MSI)
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*/
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input wire [31:0] tx_msi_wr_req_tlp_data,
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input wire tx_msi_wr_req_tlp_strb,
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input wire [TLP_HDR_WIDTH-1:0] tx_msi_wr_req_tlp_hdr,
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input wire tx_msi_wr_req_tlp_valid,
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input wire tx_msi_wr_req_tlp_sop,
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input wire tx_msi_wr_req_tlp_eop,
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output wire tx_msi_wr_req_tlp_ready,
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/*
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* Flow control
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*/
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output wire [7:0] tx_fc_ph_av,
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output wire [11:0] tx_fc_pd_av,
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output wire [7:0] tx_fc_nph_av,
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output wire [11:0] tx_fc_npd_av,
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output wire [7:0] tx_fc_cplh_av,
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output wire [11:0] tx_fc_cpld_av,
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/*
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* Configuration outputs
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*/
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output wire [F_COUNT-1:0] ext_tag_enable,
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output wire [F_COUNT-1:0] rcb_128b,
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output wire [7:0] bus_num,
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output wire [F_COUNT*3-1:0] max_read_request_size,
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output wire [F_COUNT*3-1:0] max_payload_size,
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output wire [F_COUNT-1:0] msix_enable,
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output wire [F_COUNT-1:0] msix_mask,
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/*
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* MSI request inputs
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*/
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input wire [MSI_COUNT-1:0] msi_irq
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);
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wire [PF_COUNT-1:0] cfg_msi_enable;
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wire [PF_COUNT*3-1:0] cfg_multiple_msi_enable;
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wire [PF_COUNT*32-1:0] cfg_msi_mask;
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pcie_s10_if_rx #(
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.SEG_COUNT(SEG_COUNT),
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.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
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.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
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.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.TLP_SEG_COUNT(TLP_SEG_COUNT),
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.IO_BAR_INDEX(IO_BAR_INDEX)
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)
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pcie_s10_if_rx_inst (
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.clk(clk),
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.rst(rst),
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/*
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* H-Tile/L-Tile RX AVST interface
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*/
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.rx_st_data(rx_st_data),
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.rx_st_empty(rx_st_empty),
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.rx_st_sop(rx_st_sop),
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.rx_st_eop(rx_st_eop),
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.rx_st_valid(rx_st_valid),
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.rx_st_ready(rx_st_ready),
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.rx_st_vf_active(rx_st_vf_active),
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.rx_st_func_num(rx_st_func_num),
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.rx_st_vf_num(rx_st_vf_num),
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.rx_st_bar_range(rx_st_bar_range),
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/*
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* TLP output (request to BAR)
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*/
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.rx_req_tlp_data(rx_req_tlp_data),
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.rx_req_tlp_strb(rx_req_tlp_strb),
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.rx_req_tlp_hdr(rx_req_tlp_hdr),
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.rx_req_tlp_bar_id(rx_req_tlp_bar_id),
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.rx_req_tlp_func_num(rx_req_tlp_func_num),
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.rx_req_tlp_valid(rx_req_tlp_valid),
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.rx_req_tlp_sop(rx_req_tlp_sop),
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.rx_req_tlp_eop(rx_req_tlp_eop),
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.rx_req_tlp_ready(rx_req_tlp_ready),
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/*
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* TLP output (completion to DMA)
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*/
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.rx_cpl_tlp_data(rx_cpl_tlp_data),
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.rx_cpl_tlp_strb(rx_cpl_tlp_strb),
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.rx_cpl_tlp_hdr(rx_cpl_tlp_hdr),
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.rx_cpl_tlp_error(rx_cpl_tlp_error),
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.rx_cpl_tlp_valid(rx_cpl_tlp_valid),
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.rx_cpl_tlp_sop(rx_cpl_tlp_sop),
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.rx_cpl_tlp_eop(rx_cpl_tlp_eop),
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.rx_cpl_tlp_ready(rx_cpl_tlp_ready)
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);
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pcie_s10_if_tx #(
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.SEG_COUNT(SEG_COUNT),
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.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
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.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
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.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.TLP_SEG_COUNT(TLP_SEG_COUNT),
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.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH)
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)
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pcie_s10_if_tx_inst (
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.clk(clk),
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.rst(rst),
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/*
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* H-Tile/L-Tile TX AVST interface
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*/
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.tx_st_data(tx_st_data),
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.tx_st_sop(tx_st_sop),
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.tx_st_eop(tx_st_eop),
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.tx_st_valid(tx_st_valid),
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.tx_st_ready(tx_st_ready),
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.tx_st_err(tx_st_err),
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/*
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* H-Tile/L-Tile TX flow control
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*/
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.tx_ph_cdts(tx_ph_cdts),
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.tx_pd_cdts(tx_pd_cdts),
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.tx_nph_cdts(tx_nph_cdts),
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.tx_npd_cdts(L_TILE ? tx_npd_cdts : 12'h800),
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.tx_cplh_cdts(tx_cplh_cdts),
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.tx_cpld_cdts(L_TILE ? tx_cpld_cdts : 12'h800),
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.tx_hdr_cdts_consumed(tx_hdr_cdts_consumed),
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.tx_data_cdts_consumed(tx_data_cdts_consumed),
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.tx_cdts_type(tx_cdts_type),
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.tx_cdts_data_value(tx_cdts_data_value),
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/*
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* TLP input (read request from DMA)
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*/
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.tx_rd_req_tlp_hdr(tx_rd_req_tlp_hdr),
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.tx_rd_req_tlp_seq(tx_rd_req_tlp_seq),
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.tx_rd_req_tlp_valid(tx_rd_req_tlp_valid),
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.tx_rd_req_tlp_sop(tx_rd_req_tlp_sop),
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.tx_rd_req_tlp_eop(tx_rd_req_tlp_eop),
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.tx_rd_req_tlp_ready(tx_rd_req_tlp_ready),
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/*
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* Transmit sequence number output (DMA read request)
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*/
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.m_axis_rd_req_tx_seq_num(m_axis_rd_req_tx_seq_num),
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.m_axis_rd_req_tx_seq_num_valid(m_axis_rd_req_tx_seq_num_valid),
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/*
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* TLP input (write request from DMA)
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*/
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.tx_wr_req_tlp_data(tx_wr_req_tlp_data),
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.tx_wr_req_tlp_strb(tx_wr_req_tlp_strb),
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.tx_wr_req_tlp_hdr(tx_wr_req_tlp_hdr),
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.tx_wr_req_tlp_seq(tx_wr_req_tlp_seq),
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.tx_wr_req_tlp_valid(tx_wr_req_tlp_valid),
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.tx_wr_req_tlp_sop(tx_wr_req_tlp_sop),
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.tx_wr_req_tlp_eop(tx_wr_req_tlp_eop),
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.tx_wr_req_tlp_ready(tx_wr_req_tlp_ready),
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/*
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* Transmit sequence number output (DMA write request)
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*/
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.m_axis_wr_req_tx_seq_num(m_axis_wr_req_tx_seq_num),
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.m_axis_wr_req_tx_seq_num_valid(m_axis_wr_req_tx_seq_num_valid),
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/*
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* TLP input (completion from BAR)
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*/
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.tx_cpl_tlp_data(tx_cpl_tlp_data),
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.tx_cpl_tlp_strb(tx_cpl_tlp_strb),
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.tx_cpl_tlp_hdr(tx_cpl_tlp_hdr),
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.tx_cpl_tlp_valid(tx_cpl_tlp_valid),
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.tx_cpl_tlp_sop(tx_cpl_tlp_sop),
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.tx_cpl_tlp_eop(tx_cpl_tlp_eop),
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.tx_cpl_tlp_ready(tx_cpl_tlp_ready),
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/*
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* TLP input (write request from MSI)
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*/
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.tx_msi_wr_req_tlp_data(tx_msi_wr_req_tlp_data),
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.tx_msi_wr_req_tlp_strb(tx_msi_wr_req_tlp_strb),
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.tx_msi_wr_req_tlp_hdr(tx_msi_wr_req_tlp_hdr),
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.tx_msi_wr_req_tlp_valid(tx_msi_wr_req_tlp_valid),
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.tx_msi_wr_req_tlp_sop(tx_msi_wr_req_tlp_sop),
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.tx_msi_wr_req_tlp_eop(tx_msi_wr_req_tlp_eop),
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.tx_msi_wr_req_tlp_ready(tx_msi_wr_req_tlp_ready),
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/*
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* Flow control
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*/
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.tx_fc_ph_av(tx_fc_ph_av),
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.tx_fc_pd_av(tx_fc_pd_av),
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.tx_fc_nph_av(tx_fc_nph_av),
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.tx_fc_npd_av(tx_fc_npd_av),
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.tx_fc_cplh_av(tx_fc_cplh_av),
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.tx_fc_cpld_av(tx_fc_cpld_av),
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/*
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* Configuration
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*/
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.max_payload_size(max_payload_size)
|
|
);
|
|
|
|
pcie_s10_cfg #(
|
|
.L_TILE(L_TILE),
|
|
.PF_COUNT(PF_COUNT)
|
|
)
|
|
pcie_s10_cfg_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Configuration input from H-Tile/L-Tile
|
|
*/
|
|
.tl_cfg_ctl(tl_cfg_ctl),
|
|
.tl_cfg_add(tl_cfg_add),
|
|
.tl_cfg_func(tl_cfg_func),
|
|
|
|
/*
|
|
* Configuration output
|
|
*/
|
|
.cfg_memory_space_en(),
|
|
.cfg_ido_cpl_en(),
|
|
.cfg_perr_en(),
|
|
.cfg_serr_en(),
|
|
.cfg_fatal_err_rpt_en(),
|
|
.cfg_nonfatal_err_rpt_en(),
|
|
.cfg_corr_err_rpt_en(),
|
|
.cfg_unsupported_req_rpt_en(),
|
|
.cfg_bus_master_en(),
|
|
.cfg_ext_tag_en(ext_tag_enable),
|
|
.cfg_max_read_request_size(max_read_request_size),
|
|
.cfg_max_payload_size(max_payload_size),
|
|
.cfg_ido_request_en(),
|
|
.cfg_no_snoop_en(),
|
|
.cfg_relaxed_ordering_en(),
|
|
.cfg_device_num(),
|
|
.cfg_bus_num(bus_num),
|
|
.cfg_pm_no_soft_rst(),
|
|
.cfg_rcb_ctrl(rcb_128b),
|
|
.cfg_irq_disable(),
|
|
.cfg_pcie_cap_irq_msg_num(),
|
|
.cfg_sys_pwr_ctrl(),
|
|
.cfg_sys_atten_ind_ctrl(),
|
|
.cfg_sys_pwr_ind_ctrl(),
|
|
.cfg_num_vf(),
|
|
.cfg_ats_stu(),
|
|
.cfg_ats_cache_en(),
|
|
.cfg_ari_forward_en(),
|
|
.cfg_atomic_request_en(),
|
|
.cfg_tph_st_mode(),
|
|
.cfg_tph_en(),
|
|
.cfg_vf_en(),
|
|
.cfg_an_link_speed(),
|
|
.cfg_start_vf_index(),
|
|
.cfg_msi_address(),
|
|
.cfg_msi_mask(cfg_msi_mask),
|
|
.cfg_send_f_err(),
|
|
.cfg_send_nf_err(),
|
|
.cfg_send_cor_err(),
|
|
.cfg_aer_irq_msg_num(),
|
|
.cfg_msix_func_mask(msix_mask),
|
|
.cfg_msix_enable(msix_enable),
|
|
.cfg_multiple_msi_enable(cfg_multiple_msi_enable),
|
|
.cfg_64bit_msi(),
|
|
.cfg_msi_enable(cfg_msi_enable),
|
|
.cfg_msi_data(),
|
|
.cfg_aer_uncor_err_mask(),
|
|
.cfg_aer_corr_err_mask(),
|
|
.cfg_aer_uncor_err_severity()
|
|
);
|
|
|
|
generate
|
|
|
|
if (MSI_ENABLE) begin
|
|
|
|
pcie_s10_msi #(
|
|
.MSI_COUNT(MSI_COUNT)
|
|
)
|
|
pcie_s10_msi_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Interrupt request inputs
|
|
*/
|
|
.msi_irq(msi_irq),
|
|
|
|
/*
|
|
* Interface to H-Tile/L-Tile PCIe IP core
|
|
*/
|
|
.app_msi_req(app_msi_req),
|
|
.app_msi_ack(app_msi_ack),
|
|
.app_msi_tc(app_msi_tc),
|
|
.app_msi_num(app_msi_num),
|
|
.app_msi_func_num(app_msi_func_num),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_msi_enable(cfg_msi_enable),
|
|
.cfg_multiple_msi_enable(cfg_multiple_msi_enable),
|
|
.cfg_msi_mask(cfg_msi_mask)
|
|
);
|
|
|
|
end else begin
|
|
|
|
assign app_msi_req = 0;
|
|
assign app_msi_tc = 0;
|
|
assign app_msi_num = 0;
|
|
assign app_msi_func_num = 0;
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
`resetall
|