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335 lines
12 KiB
Verilog
335 lines
12 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PCIe TLP demultiplexer
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*/
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module pcie_tlp_demux #
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(
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// Output count
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parameter PORTS = 2,
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// TLP data width
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parameter TLP_DATA_WIDTH = 256,
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// TLP strobe width
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parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// Sequence number width
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parameter SEQ_NUM_WIDTH = 6,
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// TLP segment count (input)
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parameter IN_TLP_SEG_COUNT = 1,
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// TLP segment count (output)
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parameter OUT_TLP_SEG_COUNT = IN_TLP_SEG_COUNT,
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// Include output FIFOs
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parameter FIFO_ENABLE = 1,
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// FIFO depth
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parameter FIFO_DEPTH = 2048,
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// FIFO watermark level
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parameter FIFO_WATERMARK = FIFO_DEPTH/2
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)
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(
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input wire clk,
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input wire rst,
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/*
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* TLP input
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*/
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input wire [TLP_DATA_WIDTH-1:0] in_tlp_data,
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input wire [TLP_STRB_WIDTH-1:0] in_tlp_strb,
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input wire [IN_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr,
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input wire [IN_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] in_tlp_seq,
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input wire [IN_TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
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input wire [IN_TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
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input wire [IN_TLP_SEG_COUNT*4-1:0] in_tlp_error,
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input wire [IN_TLP_SEG_COUNT-1:0] in_tlp_valid,
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input wire [IN_TLP_SEG_COUNT-1:0] in_tlp_sop,
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input wire [IN_TLP_SEG_COUNT-1:0] in_tlp_eop,
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output wire in_tlp_ready,
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/*
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* TLP output
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*/
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output wire [PORTS*TLP_DATA_WIDTH-1:0] out_tlp_data,
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output wire [PORTS*TLP_STRB_WIDTH-1:0] out_tlp_strb,
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output wire [PORTS*OUT_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr,
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output wire [PORTS*OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq,
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output wire [PORTS*OUT_TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
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output wire [PORTS*OUT_TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
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output wire [PORTS*OUT_TLP_SEG_COUNT*4-1:0] out_tlp_error,
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output wire [PORTS*OUT_TLP_SEG_COUNT-1:0] out_tlp_valid,
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output wire [PORTS*OUT_TLP_SEG_COUNT-1:0] out_tlp_sop,
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output wire [PORTS*OUT_TLP_SEG_COUNT-1:0] out_tlp_eop,
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input wire [PORTS-1:0] out_tlp_ready,
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/*
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* Fields
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*/
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output wire [IN_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] match_tlp_hdr,
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output wire [IN_TLP_SEG_COUNT*3-1:0] match_tlp_bar_id,
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output wire [IN_TLP_SEG_COUNT*8-1:0] match_tlp_func_num,
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/*
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* Control
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*/
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input wire enable,
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input wire [IN_TLP_SEG_COUNT-1:0] drop,
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input wire [PORTS*IN_TLP_SEG_COUNT-1:0] select,
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/*
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* Status
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*/
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output wire [PORTS-1:0] fifo_half_full,
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output wire [PORTS-1:0] fifo_watermark
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);
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parameter CL_PORTS = $clog2(PORTS);
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parameter TLP_SEG_DATA_WIDTH = TLP_DATA_WIDTH / IN_TLP_SEG_COUNT;
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parameter TLP_SEG_STRB_WIDTH = TLP_STRB_WIDTH / IN_TLP_SEG_COUNT;
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parameter SEG_SEL_WIDTH = $clog2(IN_TLP_SEG_COUNT);
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// check configuration
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initial begin
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if (!FIFO_ENABLE && IN_TLP_SEG_COUNT != OUT_TLP_SEG_COUNT) begin
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$error("Error: Output FIFO must be enabled for segment count adaptation (instance %m)");
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$finish;
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end
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if (TLP_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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if (TLP_STRB_WIDTH*32 != TLP_DATA_WIDTH) begin
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$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
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$finish;
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end
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end
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reg [CL_PORTS-1:0] select_reg = 0, select_ctl, select_next;
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reg drop_reg = 1'b0, drop_ctl, drop_next;
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reg frame_reg = 1'b0, frame_ctl, frame_next;
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reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0, out_tlp_data_next;
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reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0, out_tlp_strb_next;
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reg [IN_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0, out_tlp_hdr_next;
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reg [IN_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq_reg = 0, out_tlp_seq_next;
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reg [IN_TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0, out_tlp_bar_id_next;
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reg [IN_TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0, out_tlp_func_num_next;
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reg [IN_TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0, out_tlp_error_next;
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reg [PORTS*IN_TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 0, out_tlp_valid_next;
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reg [IN_TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0, out_tlp_sop_next;
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reg [IN_TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0, out_tlp_eop_next;
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wire [PORTS-1:0] out_tlp_ready_int;
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assign in_tlp_ready = (!out_tlp_valid_reg || &out_tlp_ready_int) && enable;
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assign match_tlp_hdr = in_tlp_hdr;
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assign match_tlp_bar_id = in_tlp_bar_id;
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assign match_tlp_func_num = in_tlp_func_num;
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generate
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genvar n;
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if (FIFO_ENABLE) begin
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for (n = 0; n < PORTS; n = n + 1) begin
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pcie_tlp_fifo #(
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.DEPTH(FIFO_DEPTH),
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.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
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.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.SEQ_NUM_WIDTH(SEQ_NUM_WIDTH),
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.IN_TLP_SEG_COUNT(IN_TLP_SEG_COUNT),
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.OUT_TLP_SEG_COUNT(OUT_TLP_SEG_COUNT),
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.WATERMARK(FIFO_WATERMARK)
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)
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pcie_tlp_fifo_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP input
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*/
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.in_tlp_data(out_tlp_data_reg),
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.in_tlp_strb(out_tlp_strb_reg),
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.in_tlp_hdr(out_tlp_hdr_reg),
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.in_tlp_seq(out_tlp_seq_reg),
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.in_tlp_bar_id(out_tlp_bar_id_reg),
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.in_tlp_func_num(out_tlp_func_num_reg),
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.in_tlp_error(out_tlp_error_reg),
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.in_tlp_valid(out_tlp_valid_reg[IN_TLP_SEG_COUNT*n +: IN_TLP_SEG_COUNT]),
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.in_tlp_sop(out_tlp_sop_reg),
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.in_tlp_eop(out_tlp_eop_reg),
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.in_tlp_ready(out_tlp_ready_int[n +: 1]),
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/*
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* TLP output
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*/
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.out_tlp_data(out_tlp_data[TLP_DATA_WIDTH*n +: TLP_DATA_WIDTH]),
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.out_tlp_strb(out_tlp_strb[TLP_STRB_WIDTH*n +: TLP_STRB_WIDTH]),
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.out_tlp_hdr(out_tlp_hdr[OUT_TLP_SEG_COUNT*TLP_HDR_WIDTH*n +: OUT_TLP_SEG_COUNT*TLP_HDR_WIDTH]),
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.out_tlp_seq(out_tlp_seq[OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH*n +: OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH]),
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.out_tlp_bar_id(out_tlp_bar_id[OUT_TLP_SEG_COUNT*3*n +: OUT_TLP_SEG_COUNT*3]),
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.out_tlp_func_num(out_tlp_func_num[OUT_TLP_SEG_COUNT*8*n +: OUT_TLP_SEG_COUNT*8]),
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.out_tlp_error(out_tlp_error[OUT_TLP_SEG_COUNT*4*n +: OUT_TLP_SEG_COUNT*4]),
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.out_tlp_valid(out_tlp_valid[OUT_TLP_SEG_COUNT*n +: OUT_TLP_SEG_COUNT]),
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.out_tlp_sop(out_tlp_sop[OUT_TLP_SEG_COUNT*n +: OUT_TLP_SEG_COUNT]),
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.out_tlp_eop(out_tlp_eop[OUT_TLP_SEG_COUNT*n +: OUT_TLP_SEG_COUNT]),
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.out_tlp_ready(out_tlp_ready[n +: 1]),
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/*
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* Status
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*/
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.half_full(fifo_half_full[n +: 1]),
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.watermark(fifo_watermark[n +: 1])
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);
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end
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end else begin
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assign out_tlp_data = {PORTS{out_tlp_data_reg}};
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assign out_tlp_strb = {PORTS{out_tlp_strb_reg}};
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assign out_tlp_hdr = {PORTS{out_tlp_hdr_reg}};
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assign out_tlp_seq = {PORTS{out_tlp_seq_reg}};
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assign out_tlp_bar_id = {PORTS{out_tlp_bar_id_reg}};
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assign out_tlp_func_num = {PORTS{out_tlp_func_num_reg}};
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assign out_tlp_error = {PORTS{out_tlp_error_reg}};
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assign out_tlp_valid = out_tlp_valid_reg;
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assign out_tlp_sop = {PORTS{out_tlp_sop_reg}};
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assign out_tlp_eop = {PORTS{out_tlp_eop_reg}};
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assign out_tlp_ready_int = out_tlp_ready;
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assign fifo_half_full = 0;
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assign fifo_watermark = 0;
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end
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endgenerate
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integer seg, port;
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always @* begin
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select_next = select_reg;
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drop_next = drop_reg;
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frame_next = frame_reg;
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out_tlp_data_next = out_tlp_data_reg;
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out_tlp_strb_next = out_tlp_strb_reg;
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out_tlp_hdr_next = out_tlp_hdr_reg;
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out_tlp_seq_next = out_tlp_seq_reg;
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out_tlp_bar_id_next = out_tlp_bar_id_reg;
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out_tlp_func_num_next = out_tlp_func_num_reg;
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out_tlp_error_next = out_tlp_error_reg;
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out_tlp_valid_next = out_tlp_valid_reg;
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for (port = 0; port < PORTS; port = port + 1) begin
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if (out_tlp_ready_int[port]) begin
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out_tlp_valid_next[IN_TLP_SEG_COUNT*port +: IN_TLP_SEG_COUNT] = 0;
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end
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end
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out_tlp_sop_next = out_tlp_sop_reg;
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out_tlp_eop_next = out_tlp_eop_reg;
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if (in_tlp_ready) begin
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out_tlp_data_next = in_tlp_data;
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out_tlp_strb_next = in_tlp_strb;
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out_tlp_hdr_next = in_tlp_hdr;
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out_tlp_seq_next = in_tlp_seq;
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out_tlp_bar_id_next = in_tlp_bar_id;
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out_tlp_func_num_next = in_tlp_func_num;
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out_tlp_error_next = in_tlp_error;
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out_tlp_sop_next = in_tlp_sop;
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out_tlp_eop_next = in_tlp_eop;
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for (seg = 0; seg < IN_TLP_SEG_COUNT; seg = seg + 1) begin
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if (in_tlp_valid[seg]) begin
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if (in_tlp_sop[seg]) begin
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frame_next = 1'b1;
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select_next = 0;
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drop_next = 1'b1;
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for (port = 0; port < PORTS; port = port + 1) begin
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if (select[IN_TLP_SEG_COUNT*port + seg]) begin
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select_next = port;
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drop_next = 1'b0;
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end
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end
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if (drop[seg]) begin
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drop_next = 1'b1;
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end
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end
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if (frame_next && !drop_next) begin
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out_tlp_valid_next[IN_TLP_SEG_COUNT*select_next + seg] = 1'b1;
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end
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if (in_tlp_eop[seg]) begin
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frame_next = 1'b0;
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drop_next = 1'b0;
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end
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end
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end
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end
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end
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always @(posedge clk) begin
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select_reg <= select_next;
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drop_reg <= drop_next;
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frame_reg <= frame_next;
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out_tlp_data_reg <= out_tlp_data_next;
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out_tlp_strb_reg <= out_tlp_strb_next;
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out_tlp_hdr_reg <= out_tlp_hdr_next;
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out_tlp_seq_reg <= out_tlp_seq_next;
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out_tlp_bar_id_reg <= out_tlp_bar_id_next;
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out_tlp_func_num_reg <= out_tlp_func_num_next;
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out_tlp_error_reg <= out_tlp_error_next;
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out_tlp_valid_reg <= out_tlp_valid_next;
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out_tlp_sop_reg <= out_tlp_sop_next;
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out_tlp_eop_reg <= out_tlp_eop_next;
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if (rst) begin
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select_reg <= 0;
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drop_reg <= 1'b0;
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frame_reg <= 1'b0;
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out_tlp_valid_reg <= 0;
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end
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end
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endmodule
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`resetall
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