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181 lines
6.9 KiB
Verilog
181 lines
6.9 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream broadcaster
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*/
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module axis_broadcast #
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(
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parameter M_COUNT = 4,
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter LAST_ENABLE = 1,
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] s_axis_tdata,
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input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [ID_WIDTH-1:0] s_axis_tid,
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input wire [DEST_WIDTH-1:0] s_axis_tdest,
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input wire [USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI outputs
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*/
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output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
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output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire [M_COUNT-1:0] m_axis_tvalid,
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input wire [M_COUNT-1:0] m_axis_tready,
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output wire [M_COUNT-1:0] m_axis_tlast,
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output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
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output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest,
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output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser
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);
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parameter CL_M_COUNT = $clog2(M_COUNT);
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// datapath registers
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reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
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reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next;
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reg m_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
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reg temp_m_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
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// // datapath control
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reg store_axis_input_to_output;
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reg store_axis_input_to_temp;
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reg store_axis_temp_to_output;
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assign s_axis_tready = s_axis_tready_reg;
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assign m_axis_tdata = {M_COUNT{m_axis_tdata_reg}};
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assign m_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
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assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = LAST_ENABLE ? {M_COUNT{m_axis_tlast_reg}} : {M_COUNT{1'b1}};
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assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
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assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !s_axis_tvalid));
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always @* begin
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// transfer sink ready state to source
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m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready;
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temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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store_axis_input_to_output = 1'b0;
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store_axis_input_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (s_axis_tready_reg) begin
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// input is ready
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if (((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || !m_axis_tvalid) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_tvalid_next = {M_COUNT{s_axis_tvalid}};
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store_axis_input_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_tvalid_next = s_axis_tvalid;
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store_axis_input_to_temp = 1'b1;
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end
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end else if ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) begin
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// input is not ready, but output is ready
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m_axis_tvalid_next = {M_COUNT{temp_m_axis_tvalid_reg}};
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temp_m_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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s_axis_tready_reg <= 1'b0;
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m_axis_tvalid_reg <= {M_COUNT{1'b0}};
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temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
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end else begin
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s_axis_tready_reg <= s_axis_tready_early;
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m_axis_tvalid_reg <= m_axis_tvalid_next;
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temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
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end
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// datapath
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if (store_axis_input_to_output) begin
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m_axis_tdata_reg <= s_axis_tdata;
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m_axis_tkeep_reg <= s_axis_tkeep;
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m_axis_tlast_reg <= s_axis_tlast;
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m_axis_tid_reg <= s_axis_tid;
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m_axis_tdest_reg <= s_axis_tdest;
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m_axis_tuser_reg <= s_axis_tuser;
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end else if (store_axis_temp_to_output) begin
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m_axis_tdata_reg <= temp_m_axis_tdata_reg;
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m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
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m_axis_tlast_reg <= temp_m_axis_tlast_reg;
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m_axis_tid_reg <= temp_m_axis_tid_reg;
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m_axis_tdest_reg <= temp_m_axis_tdest_reg;
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m_axis_tuser_reg <= temp_m_axis_tuser_reg;
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end
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if (store_axis_input_to_temp) begin
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temp_m_axis_tdata_reg <= s_axis_tdata;
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temp_m_axis_tkeep_reg <= s_axis_tkeep;
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temp_m_axis_tlast_reg <= s_axis_tlast;
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temp_m_axis_tid_reg <= s_axis_tid;
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temp_m_axis_tdest_reg <= s_axis_tdest;
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temp_m_axis_tuser_reg <= s_axis_tuser;
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end
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end
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endmodule
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