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406 lines
16 KiB
Verilog
406 lines
16 KiB
Verilog
/*
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Copyright (c) 2013-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream FIFO
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*/
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module axis_fifo #
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(
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// FIFO depth in words
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// KEEP_WIDTH words per cycle if KEEP_ENABLE set
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// Rounded up to nearest power of 2 cycles
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parameter DEPTH = 4096,
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// Width of AXI stream interfaces in bits
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parameter DATA_WIDTH = 8,
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// Propagate tkeep signal
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// If disabled, tkeep assumed to be 1'b1
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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// tkeep signal width (words per cycle)
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parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
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// Propagate tlast signal
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parameter LAST_ENABLE = 1,
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// Propagate tid signal
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parameter ID_ENABLE = 0,
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// tid signal width
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parameter ID_WIDTH = 8,
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// Propagate tdest signal
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parameter DEST_ENABLE = 0,
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// tdest signal width
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parameter DEST_WIDTH = 8,
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// Propagate tuser signal
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parameter USER_ENABLE = 1,
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// tuser signal width
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parameter USER_WIDTH = 1,
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// number of RAM pipeline registers
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parameter RAM_PIPELINE = 1,
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// use output FIFO
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// When set, the RAM read enable and pipeline clock enables are removed
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parameter OUTPUT_FIFO_ENABLE = 0,
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// Frame FIFO mode - operate on frames instead of cycles
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// When set, m_axis_tvalid will not be deasserted within a frame
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// Requires LAST_ENABLE set
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parameter FRAME_FIFO = 0,
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// tuser value for bad frame marker
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parameter USER_BAD_FRAME_VALUE = 1'b1,
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// tuser mask for bad frame marker
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parameter USER_BAD_FRAME_MASK = 1'b1,
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// Drop frames larger than FIFO
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// Requires FRAME_FIFO set
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parameter DROP_OVERSIZE_FRAME = FRAME_FIFO,
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// Drop frames marked bad
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// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
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parameter DROP_BAD_FRAME = 0,
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// Drop incoming frames when full
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// When set, s_axis_tready is always asserted
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// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
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parameter DROP_WHEN_FULL = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] s_axis_tdata,
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input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [ID_WIDTH-1:0] s_axis_tid,
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input wire [DEST_WIDTH-1:0] s_axis_tdest,
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input wire [USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] m_axis_tdata,
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output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [ID_WIDTH-1:0] m_axis_tid,
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output wire [DEST_WIDTH-1:0] m_axis_tdest,
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output wire [USER_WIDTH-1:0] m_axis_tuser,
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/*
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* Status
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*/
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output wire status_overflow,
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output wire status_bad_frame,
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output wire status_good_frame
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);
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parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
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parameter OUTPUT_FIFO_ADDR_WIDTH = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
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// check configuration
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initial begin
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if (FRAME_FIFO && !LAST_ENABLE) begin
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$error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
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$finish;
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end
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if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin
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$error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
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$finish;
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end
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if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
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$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
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$finish;
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end
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if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
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$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
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$finish;
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end
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if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
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$error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
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$finish;
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end
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end
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localparam KEEP_OFFSET = DATA_WIDTH;
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localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
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localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
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localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
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localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
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localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
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reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
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(* ramstyle = "no_rw_check" *)
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reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
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reg mem_read_data_valid_reg = 1'b0;
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(* shreg_extract = "no" *)
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reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0];
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reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0;
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// full when first MSB different but rest same
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wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
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wire full_cur = wr_ptr_cur_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
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// empty when pointers match exactly
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wire empty = wr_ptr_reg == rd_ptr_reg;
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// overflow within packet
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wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
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reg drop_frame_reg = 1'b0;
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reg send_frame_reg = 1'b0;
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reg overflow_reg = 1'b0;
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reg bad_frame_reg = 1'b0;
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reg good_frame_reg = 1'b0;
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assign s_axis_tready = FRAME_FIFO ? (!full_cur || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : !full;
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wire [WIDTH-1:0] s_axis;
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generate
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assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
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if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
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if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
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if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid;
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if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
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if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser;
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endgenerate
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wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1];
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wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1];
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wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0];
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wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
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wire m_axis_tlast_pipe = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1;
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wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
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wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
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wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
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wire pipe_ready;
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assign status_overflow = overflow_reg;
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assign status_bad_frame = bad_frame_reg;
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assign status_good_frame = good_frame_reg;
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// Write logic
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always @(posedge clk) begin
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overflow_reg <= 1'b0;
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bad_frame_reg <= 1'b0;
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good_frame_reg <= 1'b0;
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if (s_axis_tready && s_axis_tvalid) begin
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// transfer in
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if (!FRAME_FIFO) begin
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// normal FIFO mode
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mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
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wr_ptr_reg <= wr_ptr_reg + 1;
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end else if ((full_cur && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
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// full, packet overflow, or currently dropping frame
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// drop frame
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drop_frame_reg <= 1'b1;
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if (s_axis_tlast) begin
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// end of frame, reset write pointer
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wr_ptr_cur_reg <= wr_ptr_reg;
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drop_frame_reg <= 1'b0;
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overflow_reg <= 1'b1;
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end
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end else begin
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// store it
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mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis;
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wr_ptr_cur_reg <= wr_ptr_cur_reg + 1;
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if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
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// end of frame or send frame
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send_frame_reg <= !s_axis_tlast;
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if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
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// bad packet, reset write pointer
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wr_ptr_cur_reg <= wr_ptr_reg;
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bad_frame_reg <= 1'b1;
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end else begin
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// good packet or packet overflow, update write pointer
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wr_ptr_reg <= wr_ptr_cur_reg + 1;
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good_frame_reg <= s_axis_tlast;
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end
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end
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end
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end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
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// data valid with packet overflow
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// update write pointer
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send_frame_reg <= 1'b1;
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wr_ptr_reg <= wr_ptr_cur_reg;
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end
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if (rst) begin
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wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
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drop_frame_reg <= 1'b0;
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send_frame_reg <= 1'b0;
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overflow_reg <= 1'b0;
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bad_frame_reg <= 1'b0;
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good_frame_reg <= 1'b0;
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end
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end
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// Read logic
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integer j;
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always @(posedge clk) begin
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if (OUTPUT_FIFO_ENABLE || m_axis_tready) begin
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// output ready; invalidate stage
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m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
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end
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for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
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if (OUTPUT_FIFO_ENABLE || m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin
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// output ready or bubble in pipeline; transfer down pipeline
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m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
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m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
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m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
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end
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end
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if (OUTPUT_FIFO_ENABLE || m_axis_tready || ~m_axis_tvalid_pipe_reg) begin
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// output ready or bubble in pipeline; read new data from FIFO
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m_axis_tvalid_pipe_reg[0] <= 1'b0;
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m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
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if (!empty && pipe_ready) begin
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// not empty, increment pointer
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m_axis_tvalid_pipe_reg[0] <= 1'b1;
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rd_ptr_reg <= rd_ptr_reg + 1;
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end
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end
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if (rst) begin
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rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
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m_axis_tvalid_pipe_reg <= 0;
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end
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end
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generate
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if (!OUTPUT_FIFO_ENABLE) begin
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assign pipe_ready = 1'b1;
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assign m_axis_tvalid = m_axis_tvalid_pipe;
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assign m_axis_tdata = m_axis_tdata_pipe;
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assign m_axis_tkeep = m_axis_tkeep_pipe;
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assign m_axis_tlast = m_axis_tlast_pipe;
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assign m_axis_tid = m_axis_tid_pipe;
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assign m_axis_tdest = m_axis_tdest_pipe;
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assign m_axis_tuser = m_axis_tuser_pipe;
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end else begin
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// output datapath logic
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reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg m_axis_tvalid_reg = 1'b0;
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reg m_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
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reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
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reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
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reg out_fifo_half_full_reg = 1'b0;
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wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
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wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
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assign pipe_ready = !out_fifo_half_full_reg;
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assign m_axis_tdata = m_axis_tdata_reg;
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assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
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assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
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assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
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always @(posedge clk) begin
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m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready;
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out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
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if (!out_fifo_full && m_axis_tvalid_pipe) begin
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out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_pipe;
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out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_pipe;
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out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_pipe;
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out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_pipe;
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out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_pipe;
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out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_pipe;
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out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
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end
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if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready)) begin
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m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
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m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
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m_axis_tvalid_reg <= 1'b1;
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m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
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m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
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m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
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m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
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out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
|
end
|
|
|
|
if (rst) begin
|
|
out_fifo_wr_ptr_reg <= 0;
|
|
out_fifo_rd_ptr_reg <= 0;
|
|
m_axis_tvalid_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
`resetall
|