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202 lines
7.0 KiB
Verilog
202 lines
7.0 KiB
Verilog
/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream rate limiter (64 bit datapath)
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*/
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module axis_rate_limit_64 #
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(
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parameter DATA_WIDTH = 64,
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parameter KEEP_WIDTH = (DATA_WIDTH/8)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser,
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/*
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* Configuration
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*/
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input wire [7:0] rate_num,
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input wire [7:0] rate_denom,
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input wire rate_by_frame
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);
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// internal datapath
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reg [DATA_WIDTH-1:0] output_axis_tdata_int;
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int = 0;
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reg output_axis_tlast_int;
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reg output_axis_tuser_int;
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wire output_axis_tready_int_early;
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reg [23:0] acc_reg = 0, acc_next;
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reg pause;
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reg frame_reg = 0, frame_next;
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reg input_axis_tready_reg = 0, input_axis_tready_next;
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assign input_axis_tready = input_axis_tready_reg;
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always @* begin
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acc_next = acc_reg;
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pause = 0;
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frame_next = frame_reg & ~input_axis_tlast;
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if (acc_reg >= rate_num) begin
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acc_next = acc_reg - rate_num;
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end
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if (input_axis_tready & input_axis_tvalid) begin
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// read input
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frame_next = ~input_axis_tlast;
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acc_next = acc_reg + (rate_denom - rate_num);
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end
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if (acc_next >= rate_num) begin
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if (rate_by_frame) begin
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pause = ~frame_next;
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end else begin
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pause = 1;
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end
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end
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input_axis_tready_next = output_axis_tready_int_early & ~pause;
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output_axis_tdata_int = input_axis_tdata;
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output_axis_tkeep_int = input_axis_tkeep;
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output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
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output_axis_tlast_int = input_axis_tlast;
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output_axis_tuser_int = input_axis_tuser;
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end
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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acc_reg <= 0;
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frame_reg <= 0;
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input_axis_tready_reg <= 0;
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end else begin
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acc_reg <= acc_next;
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frame_reg <= frame_next;
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input_axis_tready_reg <= input_axis_tready_next;
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end
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end
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// output datapath logic
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reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
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reg output_axis_tvalid_reg = 0;
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reg output_axis_tlast_reg = 0;
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reg output_axis_tuser_reg = 0;
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reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
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reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
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reg temp_axis_tvalid_reg = 0;
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reg temp_axis_tlast_reg = 0;
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reg temp_axis_tuser_reg = 0;
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assign output_axis_tdata = output_axis_tdata_reg;
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assign output_axis_tkeep = output_axis_tkeep_reg;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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assign output_axis_tlast = output_axis_tlast_reg;
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assign output_axis_tuser = output_axis_tuser_reg;
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// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
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assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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output_axis_tdata_reg <= 0;
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output_axis_tkeep_reg <= 0;
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output_axis_tvalid_reg <= 0;
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output_axis_tlast_reg <= 0;
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output_axis_tuser_reg <= 0;
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output_axis_tready_int <= 0;
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temp_axis_tdata_reg <= 0;
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temp_axis_tkeep_reg <= 0;
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temp_axis_tvalid_reg <= 0;
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temp_axis_tlast_reg <= 0;
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temp_axis_tuser_reg <= 0;
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end else begin
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// transfer sink ready state to source
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output_axis_tready_int <= output_axis_tready_int_early;
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if (output_axis_tready_int) begin
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// input is ready
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if (output_axis_tready | ~output_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_axis_tdata_reg <= output_axis_tdata_int;
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output_axis_tkeep_reg <= output_axis_tkeep_int;
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output_axis_tvalid_reg <= output_axis_tvalid_int;
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output_axis_tlast_reg <= output_axis_tlast_int;
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output_axis_tuser_reg <= output_axis_tuser_int;
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end else begin
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// output is not ready, store input in temp
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temp_axis_tdata_reg <= output_axis_tdata_int;
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temp_axis_tkeep_reg <= output_axis_tkeep_int;
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temp_axis_tvalid_reg <= output_axis_tvalid_int;
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temp_axis_tlast_reg <= output_axis_tlast_int;
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temp_axis_tuser_reg <= output_axis_tuser_int;
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end
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end else if (output_axis_tready) begin
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// input is not ready, but output is ready
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output_axis_tdata_reg <= temp_axis_tdata_reg;
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output_axis_tkeep_reg <= temp_axis_tkeep_reg;
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output_axis_tvalid_reg <= temp_axis_tvalid_reg;
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output_axis_tlast_reg <= temp_axis_tlast_reg;
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output_axis_tuser_reg <= temp_axis_tuser_reg;
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temp_axis_tdata_reg <= 0;
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temp_axis_tkeep_reg <= 0;
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temp_axis_tvalid_reg <= 0;
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temp_axis_tlast_reg <= 0;
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temp_axis_tuser_reg <= 0;
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end
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end
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end
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endmodule
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