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287 lines
11 KiB
Verilog
287 lines
11 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2019-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Completion operation mux
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*/
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module cpl_op_mux #
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(
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// Number of ports
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parameter PORTS = 2,
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// Select field width
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parameter SELECT_WIDTH = 1,
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// Queue index width
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parameter QUEUE_INDEX_WIDTH = 4,
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// Input request tag field width
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parameter S_REQ_TAG_WIDTH = 8,
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// Output request tag field width (towards descriptor module)
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// Additional bits required for response routing
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parameter M_REQ_TAG_WIDTH = S_REQ_TAG_WIDTH+$clog2(PORTS),
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// Completion size (bytes)
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parameter CPL_SIZE = 32,
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// select round robin arbitration
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parameter ARB_TYPE_ROUND_ROBIN = 0,
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// LSB priority selection
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parameter ARB_LSB_HIGH_PRIORITY = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Completion request output (to completion module)
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*/
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output wire [SELECT_WIDTH-1:0] m_axis_req_sel,
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_req_queue,
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output wire [M_REQ_TAG_WIDTH-1:0] m_axis_req_tag,
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output wire [CPL_SIZE*8-1:0] m_axis_req_data,
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output wire m_axis_req_valid,
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input wire m_axis_req_ready,
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/*
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* Completion request status input (from completion module)
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*/
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input wire [M_REQ_TAG_WIDTH-1:0] s_axis_req_status_tag,
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input wire s_axis_req_status_full,
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input wire s_axis_req_status_error,
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input wire s_axis_req_status_valid,
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/*
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* Completion request input
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*/
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input wire [PORTS*SELECT_WIDTH-1:0] s_axis_req_sel,
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input wire [PORTS*QUEUE_INDEX_WIDTH-1:0] s_axis_req_queue,
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input wire [PORTS*S_REQ_TAG_WIDTH-1:0] s_axis_req_tag,
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input wire [PORTS*CPL_SIZE*8-1:0] s_axis_req_data,
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input wire [PORTS-1:0] s_axis_req_valid,
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output wire [PORTS-1:0] s_axis_req_ready,
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/*
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* Completion request status output
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*/
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output wire [PORTS*S_REQ_TAG_WIDTH-1:0] m_axis_req_status_tag,
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output wire [PORTS-1:0] m_axis_req_status_full,
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output wire [PORTS-1:0] m_axis_req_status_error,
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output wire [PORTS-1:0] m_axis_req_status_valid
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);
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parameter CL_PORTS = $clog2(PORTS);
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// check configuration
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initial begin
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if (M_REQ_TAG_WIDTH < S_REQ_TAG_WIDTH+$clog2(PORTS)) begin
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$error("Error: M_REQ_TAG_WIDTH must be at least $clog2(PORTS) larger than S_REQ_TAG_WIDTH (instance %m)");
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$finish;
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end
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end
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// request mux
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wire [PORTS-1:0] request;
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wire [PORTS-1:0] acknowledge;
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wire [PORTS-1:0] grant;
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wire grant_valid;
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wire [CL_PORTS-1:0] grant_encoded;
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// input registers to pipeline arbitration delay
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reg [PORTS*SELECT_WIDTH-1:0] s_axis_req_sel_reg = 0;
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reg [PORTS*QUEUE_INDEX_WIDTH-1:0] s_axis_req_queue_reg = 0;
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reg [PORTS*S_REQ_TAG_WIDTH-1:0] s_axis_req_tag_reg = 0;
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reg [PORTS*CPL_SIZE*8-1:0] s_axis_req_data_reg = 0;
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reg [PORTS-1:0] s_axis_req_valid_reg = 0;
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// internal datapath
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reg [SELECT_WIDTH-1:0] m_axis_req_sel_int;
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reg [QUEUE_INDEX_WIDTH-1:0] m_axis_req_queue_int;
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reg [M_REQ_TAG_WIDTH-1:0] m_axis_req_tag_int;
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reg [CPL_SIZE*8-1:0] m_axis_req_data_int;
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reg m_axis_req_valid_int;
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reg m_axis_req_ready_int_reg = 1'b0;
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wire m_axis_req_ready_int_early;
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assign s_axis_req_ready = ~s_axis_req_valid_reg | ({PORTS{m_axis_req_ready_int_reg}} & grant);
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// mux for incoming packet
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wire [SELECT_WIDTH-1:0] current_s_desc_sel = s_axis_req_sel_reg[grant_encoded*SELECT_WIDTH +: SELECT_WIDTH];
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wire [QUEUE_INDEX_WIDTH-1:0] current_s_desc_queue = s_axis_req_queue_reg[grant_encoded*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH];
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wire [S_REQ_TAG_WIDTH-1:0] current_s_desc_tag = s_axis_req_tag_reg[grant_encoded*S_REQ_TAG_WIDTH +: S_REQ_TAG_WIDTH];
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wire [CPL_SIZE*8-1:0] current_s_desc_data = s_axis_req_data_reg[grant_encoded*CPL_SIZE*8 +: CPL_SIZE*8];
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wire current_s_desc_valid = s_axis_req_valid_reg[grant_encoded];
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wire current_s_desc_ready = s_axis_req_ready[grant_encoded];
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// arbiter instance
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arbiter #(
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.PORTS(PORTS),
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.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
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.ARB_BLOCK(1),
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.ARB_BLOCK_ACK(1),
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.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.request(request),
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.acknowledge(acknowledge),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_encoded(grant_encoded)
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);
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assign request = (s_axis_req_valid_reg & ~grant) | (s_axis_req_valid & grant);
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assign acknowledge = grant & s_axis_req_valid_reg & {PORTS{m_axis_req_ready_int_reg}};
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always @* begin
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// pass through selected packet data
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m_axis_req_sel_int = current_s_desc_sel;
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m_axis_req_queue_int = current_s_desc_queue;
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m_axis_req_tag_int = {grant_encoded, current_s_desc_tag};
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m_axis_req_data_int = current_s_desc_data;
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m_axis_req_valid_int = current_s_desc_valid && m_axis_req_ready_int_reg && grant_valid;
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end
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integer i;
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always @(posedge clk) begin
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// register inputs
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for (i = 0; i < PORTS; i = i + 1) begin
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if (s_axis_req_ready[i]) begin
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s_axis_req_sel_reg[i*SELECT_WIDTH +: SELECT_WIDTH] <= s_axis_req_sel[i*SELECT_WIDTH +: SELECT_WIDTH];
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s_axis_req_queue_reg[i*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH] <= s_axis_req_queue[i*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH];
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s_axis_req_tag_reg[i*S_REQ_TAG_WIDTH +: S_REQ_TAG_WIDTH] <= s_axis_req_tag[i*S_REQ_TAG_WIDTH +: S_REQ_TAG_WIDTH];
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s_axis_req_data_reg[i*CPL_SIZE*8 +: CPL_SIZE*8] <= s_axis_req_data[i*CPL_SIZE*8 +: CPL_SIZE*8];
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s_axis_req_valid_reg[i] <= s_axis_req_valid[i];
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end
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end
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if (rst) begin
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s_axis_req_valid_reg <= 0;
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end
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end
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// output datapath logic
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reg [SELECT_WIDTH-1:0] m_axis_req_sel_reg = {SELECT_WIDTH{1'b0}};
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reg [QUEUE_INDEX_WIDTH-1:0] m_axis_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}};
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reg [M_REQ_TAG_WIDTH-1:0] m_axis_req_tag_reg = {M_REQ_TAG_WIDTH{1'b0}};
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reg [CPL_SIZE*8-1:0] m_axis_req_data_reg = {CPL_SIZE*8{1'b0}};
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reg m_axis_req_valid_reg = 1'b0, m_axis_req_valid_next;
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reg [SELECT_WIDTH-1:0] temp_m_axis_req_sel_reg = {SELECT_WIDTH{1'b0}};
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reg [QUEUE_INDEX_WIDTH-1:0] temp_m_axis_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}};
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reg [M_REQ_TAG_WIDTH-1:0] temp_m_axis_req_tag_reg = {M_REQ_TAG_WIDTH{1'b0}};
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reg [CPL_SIZE*8-1:0] temp_m_axis_req_data_reg = {CPL_SIZE*8{1'b0}};
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reg temp_m_axis_req_valid_reg = 1'b0, temp_m_axis_req_valid_next;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign m_axis_req_sel = m_axis_req_sel_reg;
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assign m_axis_req_queue = m_axis_req_queue_reg;
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assign m_axis_req_tag = m_axis_req_tag_reg;
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assign m_axis_req_data = m_axis_req_data_reg;
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assign m_axis_req_valid = m_axis_req_valid_reg;
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// enable ready input next cycle if output is ready or if both output registers are empty
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assign m_axis_req_ready_int_early = m_axis_req_ready || (!temp_m_axis_req_valid_reg && !m_axis_req_valid_reg);
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always @* begin
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// transfer sink ready state to source
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m_axis_req_valid_next = m_axis_req_valid_reg;
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temp_m_axis_req_valid_next = temp_m_axis_req_valid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (m_axis_req_ready_int_reg) begin
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// input is ready
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if (m_axis_req_ready || !m_axis_req_valid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_req_valid_next = m_axis_req_valid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_req_valid_next = m_axis_req_valid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis_req_ready) begin
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// input is not ready, but output is ready
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m_axis_req_valid_next = temp_m_axis_req_valid_reg;
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temp_m_axis_req_valid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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m_axis_req_valid_reg <= m_axis_req_valid_next;
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m_axis_req_ready_int_reg <= m_axis_req_ready_int_early;
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temp_m_axis_req_valid_reg <= temp_m_axis_req_valid_next;
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// datapath
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if (store_axis_int_to_output) begin
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m_axis_req_sel_reg <= m_axis_req_sel_int;
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m_axis_req_queue_reg <= m_axis_req_queue_int;
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m_axis_req_tag_reg <= m_axis_req_tag_int;
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m_axis_req_data_reg <= m_axis_req_data_int;
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end else if (store_axis_temp_to_output) begin
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m_axis_req_sel_reg <= temp_m_axis_req_sel_reg;
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m_axis_req_queue_reg <= temp_m_axis_req_queue_reg;
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m_axis_req_tag_reg <= temp_m_axis_req_tag_reg;
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m_axis_req_data_reg <= temp_m_axis_req_data_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_m_axis_req_sel_reg <= m_axis_req_sel_int;
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temp_m_axis_req_queue_reg <= m_axis_req_queue_int;
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temp_m_axis_req_tag_reg <= m_axis_req_tag_int;
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temp_m_axis_req_data_reg <= m_axis_req_data_int;
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end
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if (rst) begin
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m_axis_req_valid_reg <= 1'b0;
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m_axis_req_ready_int_reg <= 1'b0;
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temp_m_axis_req_valid_reg <= 1'b0;
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end
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end
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// request status demux
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reg [S_REQ_TAG_WIDTH-1:0] m_axis_req_status_tag_reg = {S_REQ_TAG_WIDTH{1'b0}}, m_axis_req_status_tag_next;
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reg m_axis_req_status_full_reg = 1'b0, m_axis_req_status_full_next;
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reg m_axis_req_status_error_reg = 1'b0, m_axis_req_status_error_next;
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reg [PORTS-1:0] m_axis_req_status_valid_reg = {PORTS{1'b0}}, m_axis_req_status_valid_next;
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assign m_axis_req_status_tag = {PORTS{m_axis_req_status_tag_reg}};
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assign m_axis_req_status_full = {PORTS{m_axis_req_status_full_reg}};
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assign m_axis_req_status_error = {PORTS{m_axis_req_status_error_reg}};
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assign m_axis_req_status_valid = m_axis_req_status_valid_reg;
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always @* begin
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m_axis_req_status_tag_next = s_axis_req_status_tag;
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m_axis_req_status_full_next = s_axis_req_status_full;
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m_axis_req_status_error_next = s_axis_req_status_error;
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m_axis_req_status_valid_next = s_axis_req_status_valid << (PORTS > 1 ? (s_axis_req_status_tag >> S_REQ_TAG_WIDTH) : 0);
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end
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always @(posedge clk) begin
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m_axis_req_status_tag_reg <= m_axis_req_status_tag_next;
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m_axis_req_status_full_reg <= m_axis_req_status_full_next;
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m_axis_req_status_error_reg <= m_axis_req_status_error_next;
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m_axis_req_status_valid_reg <= m_axis_req_status_valid_next;
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if (rst) begin
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m_axis_req_status_valid_reg <= {PORTS{1'b0}};
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end
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end
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endmodule
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`resetall
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