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315 lines
8.5 KiB
Verilog
315 lines
8.5 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2021-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* NIC ingress processing
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*/
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module mqnic_ingress #
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(
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// Request tag field width
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parameter REQ_TAG_WIDTH = 8,
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// Receive queue index width
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parameter RX_QUEUE_INDEX_WIDTH = 8,
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// Enable RX RSS
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// Enable RX hashing
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parameter RX_HASH_ENABLE = 1,
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// Enable RX checksum offload
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parameter RX_CHECKSUM_ENABLE = 1,
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = 256,
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
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// AXI stream tid signal width
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parameter AXIS_ID_WIDTH = 8,
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// AXI stream tdest signal width
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parameter AXIS_DEST_WIDTH = 8,
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// AXI stream tuser signal width
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parameter S_AXIS_USER_WIDTH = 1,
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// AXI stream tuser signal width
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parameter M_AXIS_USER_WIDTH = S_AXIS_USER_WIDTH,
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// Max receive packet size
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parameter MAX_RX_SIZE = 2048
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Receive data input
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*/
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_tid,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_tdest,
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input wire [S_AXIS_USER_WIDTH-1:0] s_axis_tuser,
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/*
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* Receive data output
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*/
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_tid,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest,
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output wire [M_AXIS_USER_WIDTH-1:0] m_axis_tuser,
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/*
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* RX checksum output
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*/
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output wire [15:0] rx_csum,
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output wire rx_csum_valid,
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input wire rx_csum_ready
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);
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localparam RX_HASH_WIDTH = 32;
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localparam RX_HASH_TYPE_WIDTH = 4;
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localparam TUSER_HASH_OFFSET = S_AXIS_USER_WIDTH;
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localparam TUSER_HASH_TYPE_OFFSET = TUSER_HASH_OFFSET + (RX_HASH_ENABLE ? RX_HASH_WIDTH : 0);
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localparam INT_TUSER_WIDTH = TUSER_HASH_TYPE_OFFSET + (RX_HASH_ENABLE ? RX_HASH_TYPE_WIDTH : 0);
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generate
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wire [31:0] rx_fifo_hash;
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wire [3:0] rx_fifo_hash_type;
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wire rx_fifo_hash_ready;
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wire rx_fifo_hash_valid;
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if (RX_HASH_ENABLE) begin
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wire [31:0] rx_hash_int;
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wire [3:0] rx_hash_type_int;
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wire rx_hash_valid_int;
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rx_hash #(
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.DATA_WIDTH(AXIS_DATA_WIDTH)
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)
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rx_hash_inst (
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.clk(clk),
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.rst(rst),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid & s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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.hash_key(320'h6d5a56da255b0ec24167253d43a38fb0d0ca2bcbae7b30b477cb2da38030f20c6a42b73bbeac01fa),
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.m_axis_hash(rx_hash_int),
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.m_axis_hash_type(rx_hash_type_int),
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.m_axis_hash_valid(rx_hash_valid_int)
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);
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axis_fifo #(
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.DEPTH(32),
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.DATA_WIDTH(32+4),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(0),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(0),
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.FRAME_FIFO(0)
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)
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rx_hash_fifo (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata({rx_hash_type_int, rx_hash_int}),
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.s_axis_tkeep(0),
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.s_axis_tvalid(rx_hash_valid_int),
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.s_axis_tready(),
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.s_axis_tlast(0),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(0),
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// AXI output
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.m_axis_tdata({rx_fifo_hash_type, rx_fifo_hash}),
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.m_axis_tkeep(),
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.m_axis_tvalid(rx_fifo_hash_valid),
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.m_axis_tready(rx_fifo_hash_ready),
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.m_axis_tlast(),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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end else begin
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assign rx_fifo_hash = 32'd0;
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assign rx_fifo_hash_type = 4'd0;
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assign rx_fifo_hash_valid = 1'b0;
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end
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if (RX_CHECKSUM_ENABLE) begin
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wire [15:0] rx_csum_int;
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wire rx_csum_valid_int;
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rx_checksum #(
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.DATA_WIDTH(AXIS_DATA_WIDTH)
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)
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rx_checksum_inst (
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.clk(clk),
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.rst(rst),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid & s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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.m_axis_csum(rx_csum_int),
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.m_axis_csum_valid(rx_csum_valid_int)
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);
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axis_fifo #(
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.DEPTH(32),
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.DATA_WIDTH(16),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(0),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(0),
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.FRAME_FIFO(0)
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)
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rx_csum_fifo (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(rx_csum_int),
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.s_axis_tkeep(0),
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.s_axis_tvalid(rx_csum_valid_int),
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.s_axis_tready(),
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.s_axis_tlast(0),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(0),
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// AXI output
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.m_axis_tdata(rx_csum),
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.m_axis_tkeep(),
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.m_axis_tvalid(rx_csum_valid),
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.m_axis_tready(rx_csum_ready),
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.m_axis_tlast(),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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end else begin
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assign rx_csum = 16'd0;
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assign rx_csum_valid = 1'b0;
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end
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if (RX_HASH_ENABLE) begin
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wire [AXIS_DATA_WIDTH-1:0] fifo_axis_tdata;
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wire [AXIS_KEEP_WIDTH-1:0] fifo_axis_tkeep;
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wire fifo_axis_tvalid;
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wire fifo_axis_tready;
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wire fifo_axis_tlast;
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wire [AXIS_ID_WIDTH-1:0] fifo_axis_tid;
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wire [AXIS_DEST_WIDTH-1:0] fifo_axis_tdest;
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wire [S_AXIS_USER_WIDTH-1:0] fifo_axis_tuser;
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axis_fifo #(
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.DEPTH(AXIS_KEEP_WIDTH*32),
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.DATA_WIDTH(AXIS_DATA_WIDTH),
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.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
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.KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.LAST_ENABLE(1),
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.ID_ENABLE(1),
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.ID_WIDTH(AXIS_ID_WIDTH),
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.DEST_ENABLE(1),
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.DEST_WIDTH(AXIS_DEST_WIDTH),
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.USER_ENABLE(1),
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.USER_WIDTH(S_AXIS_USER_WIDTH),
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.FRAME_FIFO(0)
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)
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rx_hash_data_fifo (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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.s_axis_tid(s_axis_tid),
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.s_axis_tdest(s_axis_tdest),
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.s_axis_tuser(s_axis_tuser),
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// AXI output
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.m_axis_tdata(fifo_axis_tdata),
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.m_axis_tkeep(fifo_axis_tkeep),
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.m_axis_tvalid(fifo_axis_tvalid),
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.m_axis_tready(fifo_axis_tready),
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.m_axis_tlast(fifo_axis_tlast),
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.m_axis_tid(fifo_axis_tid),
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.m_axis_tdest(fifo_axis_tdest),
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.m_axis_tuser(fifo_axis_tuser),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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wire sideband_valid = rx_fifo_hash_valid;
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assign rx_fifo_hash_ready = fifo_axis_tready && fifo_axis_tvalid && fifo_axis_tlast;
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assign fifo_axis_tready = m_axis_tready && sideband_valid;
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assign m_axis_tdata = fifo_axis_tdata;
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assign m_axis_tkeep = fifo_axis_tkeep;
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assign m_axis_tvalid = fifo_axis_tvalid && sideband_valid;
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assign m_axis_tlast = fifo_axis_tlast;
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assign m_axis_tid = fifo_axis_tid;
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assign m_axis_tdest = fifo_axis_tdest;
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assign m_axis_tuser = {rx_fifo_hash_type, rx_fifo_hash, fifo_axis_tuser};
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end else begin
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// bypass
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assign m_axis_tdata = s_axis_tdata;
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assign m_axis_tkeep = s_axis_tkeep;
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assign m_axis_tvalid = s_axis_tvalid;
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assign s_axis_tready = m_axis_tready;
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assign m_axis_tlast = s_axis_tlast;
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assign m_axis_tid = s_axis_tid;
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assign m_axis_tdest = s_axis_tdest;
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assign m_axis_tuser = s_axis_tuser;
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end
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endgenerate
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endmodule
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`resetall
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