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116 lines
2.9 KiB
Verilog
116 lines
2.9 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* 10G Ethernet PHY TX
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*/
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module eth_phy_10g_tx #
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(
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parameter DATA_WIDTH = 64,
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parameter CTRL_WIDTH = (DATA_WIDTH/8),
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parameter HDR_WIDTH = 2,
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parameter BIT_REVERSE = 0,
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parameter SCRAMBLER_DISABLE = 0,
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parameter PRBS31_ENABLE = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* XGMII interface
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*/
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input wire [DATA_WIDTH-1:0] xgmii_txd,
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input wire [CTRL_WIDTH-1:0] xgmii_txc,
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/*
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* SERDES interface
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*/
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output wire [DATA_WIDTH-1:0] serdes_tx_data,
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output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
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/*
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* Configuration
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*/
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input wire tx_prbs31_enable
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);
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// bus width assertions
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initial begin
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if (DATA_WIDTH != 64) begin
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$error("Error: Interface width must be 64");
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$finish;
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end
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if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
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$error("Error: Interface requires byte (8-bit) granularity");
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$finish;
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end
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if (HDR_WIDTH != 2) begin
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$error("Error: HDR_WIDTH must be 2");
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$finish;
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end
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end
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wire [DATA_WIDTH-1:0] encoded_tx_data;
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wire [HDR_WIDTH-1:0] encoded_tx_hdr;
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xgmii_baser_enc_64 #(
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.HDR_WIDTH(HDR_WIDTH)
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)
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xgmii_baser_enc_inst (
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.clk(clk),
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.rst(rst),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.encoded_tx_data(encoded_tx_data),
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.encoded_tx_hdr(encoded_tx_hdr)
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);
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eth_phy_10g_tx_if #(
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.DATA_WIDTH(DATA_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.BIT_REVERSE(BIT_REVERSE),
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.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
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.PRBS31_ENABLE(PRBS31_ENABLE)
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)
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eth_phy_10g_tx_if_inst (
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.clk(clk),
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.rst(rst),
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.encoded_tx_data(encoded_tx_data),
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.encoded_tx_hdr(encoded_tx_hdr),
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.serdes_tx_data(serdes_tx_data),
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.serdes_tx_hdr(serdes_tx_hdr),
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.tx_prbs31_enable(tx_prbs31_enable)
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);
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endmodule
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