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63 lines
1.7 KiB
Verilog
63 lines
1.7 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog-2001
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`resetall
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`timescale 1 ns / 1 ps
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`default_nettype none
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/*
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* Synchronizes an asyncronous signal to a given clock by using a pipeline of
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* two registers.
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*/
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module sync_signal #(
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parameter WIDTH=1, // width of the input and output signals
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parameter N=2 // depth of synchronizer
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)(
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input wire clk,
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input wire [WIDTH-1:0] in,
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output wire [WIDTH-1:0] out
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);
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reg [WIDTH-1:0] sync_reg[N-1:0];
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/*
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* The synchronized output is the last register in the pipeline.
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*/
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assign out = sync_reg[N-1];
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integer k;
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always @(posedge clk) begin
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sync_reg[0] <= in;
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for (k = 1; k < N; k = k + 1) begin
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sync_reg[k] <= sync_reg[k-1];
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end
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end
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endmodule
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`resetall
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