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139 lines
3.7 KiB
Verilog
139 lines
3.7 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for arp_eth_tx_64
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*/
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module test_arp_eth_tx_64;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg s_frame_valid = 0;
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reg [47:0] s_eth_dest_mac = 0;
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reg [47:0] s_eth_src_mac = 0;
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reg [15:0] s_eth_type = 0;
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reg [15:0] s_arp_htype = 0;
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reg [15:0] s_arp_ptype = 0;
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reg [15:0] s_arp_oper = 0;
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reg [47:0] s_arp_sha = 0;
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reg [31:0] s_arp_spa = 0;
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reg [47:0] s_arp_tha = 0;
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reg [31:0] s_arp_tpa = 0;
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reg m_eth_hdr_ready = 0;
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reg m_eth_payload_axis_tready = 0;
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// Outputs
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wire s_frame_ready;
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wire m_eth_hdr_valid;
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wire [47:0] m_eth_dest_mac;
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wire [47:0] m_eth_src_mac;
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wire [15:0] m_eth_type;
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wire [63:0] m_eth_payload_axis_tdata;
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wire [7:0] m_eth_payload_axis_tkeep;
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wire m_eth_payload_axis_tvalid;
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wire m_eth_payload_axis_tlast;
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wire m_eth_payload_axis_tuser;
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wire busy;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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s_frame_valid,
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s_eth_dest_mac,
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s_eth_src_mac,
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s_eth_type,
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s_arp_htype,
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s_arp_ptype,
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s_arp_oper,
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s_arp_sha,
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s_arp_spa,
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s_arp_tha,
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s_arp_tpa,
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m_eth_hdr_ready,
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m_eth_payload_axis_tready
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);
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$to_myhdl(
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s_frame_ready,
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m_eth_hdr_valid,
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m_eth_dest_mac,
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m_eth_src_mac,
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m_eth_type,
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m_eth_payload_axis_tdata,
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m_eth_payload_axis_tkeep,
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m_eth_payload_axis_tvalid,
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m_eth_payload_axis_tlast,
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m_eth_payload_axis_tuser,
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busy
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);
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// dump file
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$dumpfile("test_arp_eth_tx_64.lxt");
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$dumpvars(0, test_arp_eth_tx_64);
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end
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arp_eth_tx_64
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UUT (
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.clk(clk),
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.rst(rst),
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// ARP frame input
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.s_frame_valid(s_frame_valid),
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.s_frame_ready(s_frame_ready),
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.s_eth_dest_mac(s_eth_dest_mac),
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.s_eth_src_mac(s_eth_src_mac),
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.s_eth_type(s_eth_type),
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.s_arp_htype(s_arp_htype),
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.s_arp_ptype(s_arp_ptype),
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.s_arp_oper(s_arp_oper),
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.s_arp_sha(s_arp_sha),
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.s_arp_spa(s_arp_spa),
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.s_arp_tha(s_arp_tha),
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.s_arp_tpa(s_arp_tpa),
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// Ethernet frame output
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.m_eth_hdr_valid(m_eth_hdr_valid),
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.m_eth_hdr_ready(m_eth_hdr_ready),
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.m_eth_dest_mac(m_eth_dest_mac),
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.m_eth_src_mac(m_eth_src_mac),
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.m_eth_type(m_eth_type),
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.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
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.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
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.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
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.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
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.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
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.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
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// Status signals
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.busy(busy)
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);
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endmodule
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