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561 lines
20 KiB
Verilog
561 lines
20 KiB
Verilog
/*
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Copyright (c) 2021-2022 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Xilinx UltraScale PCIe interface adapter (Completer Completion)
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*/
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module pcie_us_if_cc #
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(
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// Width of PCIe AXI stream interfaces in bits
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parameter AXIS_PCIE_DATA_WIDTH = 256,
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// PCIe AXI stream tkeep signal width (words per cycle)
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parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
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// PCIe AXI stream CC tuser signal width
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parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
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// CC interface TLP straddling
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parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
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// TLP data width
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parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
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// TLP strobe width
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parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI output (CC)
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*/
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output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
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output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
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output wire m_axis_cc_tvalid,
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input wire m_axis_cc_tready,
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output wire m_axis_cc_tlast,
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output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
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/*
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* TLP input (completion from BAR)
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*/
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input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
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input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
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output wire tx_cpl_tlp_ready
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);
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parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
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parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
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parameter INT_TLP_SEG_COUNT = (CC_STRADDLE && AXIS_PCIE_DATA_WIDTH >= 512) ? 2 : 1;
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parameter INT_TLP_SEG_DATA_WIDTH = TLP_DATA_WIDTH / INT_TLP_SEG_COUNT;
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parameter INT_TLP_SEG_STRB_WIDTH = TLP_STRB_WIDTH / INT_TLP_SEG_COUNT;
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parameter SEG_SEL_WIDTH = $clog2(INT_TLP_SEG_COUNT);
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// bus width assertions
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initial begin
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if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256 && AXIS_PCIE_DATA_WIDTH != 512) begin
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$error("Error: PCIe interface width must be 64, 128, 256, or 512 (instance %m)");
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$finish;
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end
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if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
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$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
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$finish;
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end
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if (AXIS_PCIE_DATA_WIDTH == 512) begin
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if (AXIS_PCIE_CC_USER_WIDTH != 81) begin
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$error("Error: PCIe CC tuser width must be 81 (instance %m)");
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$finish;
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end
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end else begin
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if (AXIS_PCIE_CC_USER_WIDTH != 33) begin
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$error("Error: PCIe CC tuser width must be 33 (instance %m)");
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$finish;
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end
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end
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if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
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$error("Error: Interface widths must match (instance %m)");
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$finish;
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end
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if (TLP_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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end
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localparam [2:0]
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TLP_FMT_3DW = 3'b000,
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TLP_FMT_4DW = 3'b001,
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TLP_FMT_3DW_DATA = 3'b010,
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TLP_FMT_4DW_DATA = 3'b011,
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TLP_FMT_PREFIX = 3'b100;
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localparam [2:0]
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CPL_STATUS_SC = 3'b000, // successful completion
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CPL_STATUS_UR = 3'b001, // unsupported request
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CPL_STATUS_CRS = 3'b010, // configuration request retry status
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CPL_STATUS_CA = 3'b100; // completer abort
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reg frame_reg = 1'b0, frame_next, frame_cyc;
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reg tlp_hdr1_reg = 1'b0, tlp_hdr1_next, tlp_hdr1_cyc;
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reg tlp_hdr2_reg = 1'b0, tlp_hdr2_next, tlp_hdr2_cyc;
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reg tlp_split1_reg = 1'b0, tlp_split1_next, tlp_split1_cyc;
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reg tlp_split2_reg = 1'b0, tlp_split2_next, tlp_split2_cyc;
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reg [SEG_SEL_WIDTH-1:0] seg_offset_cyc;
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reg [SEG_SEL_WIDTH+1-1:0] seg_count_cyc;
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reg valid, sop, eop;
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reg frame, abort;
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reg [INT_TLP_SEG_COUNT-1:0] out_sel, out_sel_cyc;
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reg [INT_TLP_SEG_COUNT-1:0] out_sop;
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reg [INT_TLP_SEG_COUNT-1:0] out_eop;
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reg [INT_TLP_SEG_COUNT-1:0] out_tlp_hdr1;
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reg [INT_TLP_SEG_COUNT-1:0] out_tlp_hdr2;
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reg [INT_TLP_SEG_COUNT-1:0] out_tlp_split1;
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reg [INT_TLP_SEG_COUNT-1:0] out_tlp_split2;
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reg [SEG_SEL_WIDTH+1-1:0] out_sel_seg[0:INT_TLP_SEG_COUNT-1];
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reg [TLP_DATA_WIDTH-1:0] out_tlp_data;
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reg [TLP_STRB_WIDTH-1:0] out_tlp_strb;
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reg [INT_TLP_SEG_COUNT-1:0] out_tlp_valid;
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reg [INT_TLP_SEG_COUNT-1:0] out_tlp_sop;
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reg [INT_TLP_SEG_COUNT-1:0] out_tlp_eop;
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reg [95:0] out_shift_tlp_data_reg = 0, out_shift_tlp_data_next;
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reg [2:0] out_shift_tlp_strb_reg = 0, out_shift_tlp_strb_next;
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reg [127:0] seg_tlp_hdr;
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reg [95:0] seg_cc_hdr;
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reg [INT_TLP_SEG_COUNT*3-1:0] eop_index;
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reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_reg = 0, m_axis_cc_tdata_next;
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reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_reg = 0, m_axis_cc_tkeep_next;
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reg m_axis_cc_tvalid_reg = 1'b0, m_axis_cc_tvalid_next;
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reg m_axis_cc_tlast_reg = 1'b0, m_axis_cc_tlast_next;
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reg [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser_reg = 0, m_axis_cc_tuser_next;
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assign m_axis_cc_tdata = m_axis_cc_tdata_reg;
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assign m_axis_cc_tkeep = m_axis_cc_tkeep_reg;
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assign m_axis_cc_tvalid = m_axis_cc_tvalid_reg;
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assign m_axis_cc_tlast = m_axis_cc_tlast_reg;
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assign m_axis_cc_tuser = m_axis_cc_tuser_reg;
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wire [TLP_DATA_WIDTH-1:0] fifo_tlp_data;
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wire [TLP_STRB_WIDTH-1:0] fifo_tlp_strb;
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wire [INT_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] fifo_tlp_hdr;
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wire [INT_TLP_SEG_COUNT-1:0] fifo_tlp_valid;
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wire [INT_TLP_SEG_COUNT-1:0] fifo_tlp_sop;
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wire [INT_TLP_SEG_COUNT-1:0] fifo_tlp_eop;
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wire [SEG_SEL_WIDTH-1:0] fifo_seg_offset;
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wire [SEG_SEL_WIDTH+1-1:0] fifo_seg_count;
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reg fifo_read_en;
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reg [SEG_SEL_WIDTH+1-1:0] fifo_read_seg_count;
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// completions
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pcie_tlp_fifo_raw #(
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.DEPTH((1024/4)*2),
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.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
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.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.SEQ_NUM_WIDTH(1),
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.IN_TLP_SEG_COUNT(TLP_SEG_COUNT),
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.OUT_TLP_SEG_COUNT(INT_TLP_SEG_COUNT),
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.CTRL_OUT_EN(0)
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)
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cpl_fifo_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP input
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*/
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.in_tlp_data(tx_cpl_tlp_data),
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.in_tlp_strb(tx_cpl_tlp_strb),
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.in_tlp_hdr(tx_cpl_tlp_hdr),
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.in_tlp_seq(0),
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.in_tlp_bar_id(0),
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.in_tlp_func_num(0),
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.in_tlp_error(0),
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.in_tlp_valid(tx_cpl_tlp_valid),
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.in_tlp_sop(tx_cpl_tlp_sop),
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.in_tlp_eop(tx_cpl_tlp_eop),
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.in_tlp_ready(tx_cpl_tlp_ready),
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/*
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* TLP output
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*/
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.out_tlp_data(fifo_tlp_data),
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.out_tlp_strb(fifo_tlp_strb),
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.out_tlp_hdr(fifo_tlp_hdr),
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.out_tlp_seq(),
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.out_tlp_bar_id(),
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.out_tlp_func_num(),
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.out_tlp_error(),
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.out_tlp_valid(fifo_tlp_valid),
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.out_tlp_sop(fifo_tlp_sop),
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.out_tlp_eop(fifo_tlp_eop),
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.out_seg_offset(fifo_seg_offset),
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.out_seg_count(fifo_seg_count),
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.out_read_en(fifo_read_en),
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.out_read_seg_count(fifo_read_seg_count),
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.out_ctrl_tlp_strb(),
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.out_ctrl_tlp_hdr(),
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.out_ctrl_tlp_valid(),
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.out_ctrl_tlp_sop(),
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.out_ctrl_tlp_eop(),
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.out_ctrl_seg_offset(),
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.out_ctrl_seg_count(),
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.out_ctrl_read_en(0),
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.out_ctrl_read_seg_count(0),
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/*
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* Status
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*/
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.half_full(),
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.watermark()
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);
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integer seg, cur_seg, lane;
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always @* begin
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frame_next = frame_reg;
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tlp_hdr1_next = tlp_hdr1_reg;
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tlp_hdr2_next = tlp_hdr2_reg;
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tlp_split1_next = tlp_split1_reg;
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tlp_split2_next = tlp_split2_reg;
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m_axis_cc_tdata_next = m_axis_cc_tdata_reg;
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m_axis_cc_tkeep_next = m_axis_cc_tkeep_reg;
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m_axis_cc_tvalid_next = m_axis_cc_tvalid_reg && !m_axis_cc_tready;
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m_axis_cc_tlast_next = m_axis_cc_tlast_reg;
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m_axis_cc_tuser_next = m_axis_cc_tuser_reg;
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fifo_read_en = 0;
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frame_cyc = frame_reg;
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tlp_hdr1_cyc = tlp_hdr1_reg;
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tlp_hdr2_cyc = tlp_hdr2_reg;
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tlp_split1_cyc = tlp_split1_reg;
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tlp_split2_cyc = tlp_split2_reg;
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seg_offset_cyc = fifo_seg_offset;
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seg_count_cyc = 0;
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valid = 0;
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eop = 0;
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frame = frame_cyc;
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abort = 0;
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fifo_read_seg_count = 0;
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out_sel = 0;
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out_sel_cyc = 0;
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out_sop = 0;
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out_eop = 0;
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out_tlp_hdr1 = 0;
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out_tlp_hdr2 = 0;
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out_tlp_split1 = 0;
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out_tlp_split2 = 0;
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for (seg = 0; seg < INT_TLP_SEG_COUNT; seg = seg + 1) begin
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out_sel_seg[seg] = 0;
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end
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out_shift_tlp_data_next = out_shift_tlp_data_reg;
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out_shift_tlp_strb_next = out_shift_tlp_strb_reg;
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// compute mux settings
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for (seg = 0; seg < INT_TLP_SEG_COUNT; seg = seg + 1) begin
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if (!frame_cyc && !abort) begin
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tlp_hdr1_cyc = 1'b1;
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tlp_hdr2_cyc = 1'b0;
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tlp_split1_cyc = 1'b0;
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tlp_split2_cyc = 1'b0;
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if (fifo_tlp_valid[seg_offset_cyc]) begin
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frame_cyc = 1'b1;
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end
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end
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// route segment
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valid = fifo_tlp_valid[seg_offset_cyc];
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sop = fifo_tlp_sop[seg_offset_cyc];
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eop = fifo_tlp_eop[seg_offset_cyc];
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frame = frame_cyc;
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out_sel_cyc[seg] = 1'b1;
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out_sop[seg] = tlp_hdr1_cyc;
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out_sel_seg[seg] = seg_offset_cyc;
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out_tlp_hdr1[seg] = tlp_hdr1_cyc;
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out_tlp_hdr2[seg] = tlp_hdr2_cyc;
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if (AXIS_PCIE_DATA_WIDTH == 64 && tlp_hdr1_cyc) begin
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// output header
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tlp_hdr1_cyc = 1'b0;
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tlp_hdr2_cyc = 1'b1;
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end else if (eop && fifo_tlp_strb[seg_offset_cyc*INT_TLP_SEG_STRB_WIDTH +: INT_TLP_SEG_STRB_WIDTH] >> (INT_TLP_SEG_STRB_WIDTH-(AXIS_PCIE_DATA_WIDTH == 64 ? 1 : 3))) begin
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// extra cycle
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tlp_hdr1_cyc = 1'b0;
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tlp_hdr2_cyc = 1'b0;
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if (tlp_split1_cyc) begin
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frame_cyc = 0;
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out_eop[seg] = 1'b1;
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tlp_split1_cyc = 1'b0;
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tlp_split2_cyc = 1'b1;
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seg_offset_cyc = seg_offset_cyc + 1;
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seg_count_cyc = seg_count_cyc + 1;
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end else begin
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tlp_split1_cyc = 1'b1;
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end
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end else begin
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tlp_hdr1_cyc = 1'b0;
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tlp_hdr2_cyc = 1'b0;
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if (eop) begin
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// end of packet
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frame_cyc = 0;
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out_eop[seg] = 1'b1;
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end
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seg_offset_cyc = seg_offset_cyc + 1;
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seg_count_cyc = seg_count_cyc + 1;
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end
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out_tlp_split1[seg] = tlp_split1_cyc;
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out_tlp_split2[seg] = tlp_split2_cyc;
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if (frame && !abort) begin
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if (valid) begin
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if (eop || seg == INT_TLP_SEG_COUNT-1) begin
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// end of packet or end of cycle, commit
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fifo_read_seg_count = seg_count_cyc;
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if (!m_axis_cc_tvalid || m_axis_cc_tready) begin
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frame_next = frame_cyc;
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tlp_hdr1_next = tlp_hdr1_cyc;
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tlp_hdr2_next = tlp_hdr2_cyc;
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tlp_split1_next = tlp_split1_cyc;
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tlp_split2_next = tlp_split2_cyc;
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out_sel = out_sel_cyc;
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fifo_read_en = seg_count_cyc != 0;
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end
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end
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end else begin
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// input has stalled, wait
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abort = 1;
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end
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end
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end
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out_tlp_data = 0;
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out_tlp_strb = 0;
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out_tlp_valid = 0;
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out_tlp_sop = 0;
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out_tlp_eop = 0;
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for (seg = 0; seg < INT_TLP_SEG_COUNT; seg = seg + 1) begin
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// remap header
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seg_tlp_hdr = fifo_tlp_hdr[out_sel_seg[seg]*TLP_HDR_WIDTH +: TLP_HDR_WIDTH];
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seg_cc_hdr[6:0] = seg_tlp_hdr[38:32]; // lower address
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seg_cc_hdr[7] = 1'b0;
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seg_cc_hdr[9:8] = seg_tlp_hdr[107:106]; // AT
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seg_cc_hdr[15:10] = 6'd0;
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seg_cc_hdr[28:16] = seg_tlp_hdr[75:64]; // Byte count
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seg_cc_hdr[29] = 1'b0; // locked read completion
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seg_cc_hdr[31:30] = 2'd0;
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seg_cc_hdr[42:32] = seg_tlp_hdr[105:96]; // DWORD count
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seg_cc_hdr[45:43] = seg_tlp_hdr[79:77]; // completion status
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seg_cc_hdr[46] = seg_tlp_hdr[110]; // poisoned
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seg_cc_hdr[47] = 1'b0;
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seg_cc_hdr[63:48] = seg_tlp_hdr[63:48]; // requester ID
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seg_cc_hdr[71:64] = seg_tlp_hdr[47:40]; // tag
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seg_cc_hdr[87:72] = seg_tlp_hdr[95:80]; // completer ID
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seg_cc_hdr[88] = 1'b0; // completer ID enable
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seg_cc_hdr[91:89] = seg_tlp_hdr[118:116]; // TC
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seg_cc_hdr[94:92] = {seg_tlp_hdr[114], seg_tlp_hdr[109:108]}; // attr
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seg_cc_hdr[95] = 1'b0; // force ECRC
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|
|
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// mux for output segments
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|
if (AXIS_PCIE_DATA_WIDTH == 64) begin
|
|
out_tlp_data[seg*INT_TLP_SEG_DATA_WIDTH +: INT_TLP_SEG_DATA_WIDTH] = out_shift_tlp_data_next;
|
|
out_tlp_strb[seg*INT_TLP_SEG_STRB_WIDTH +: INT_TLP_SEG_STRB_WIDTH] = out_shift_tlp_strb_next;
|
|
out_tlp_data[seg*INT_TLP_SEG_DATA_WIDTH+32 +: INT_TLP_SEG_DATA_WIDTH-32] = fifo_tlp_data[out_sel_seg[seg]*INT_TLP_SEG_DATA_WIDTH +: INT_TLP_SEG_DATA_WIDTH-32];
|
|
if (!out_tlp_split2[seg]) begin
|
|
out_tlp_strb[seg*INT_TLP_SEG_STRB_WIDTH+1 +: INT_TLP_SEG_STRB_WIDTH-1] = fifo_tlp_strb[out_sel_seg[seg]*INT_TLP_SEG_STRB_WIDTH +: INT_TLP_SEG_STRB_WIDTH-1];
|
|
end
|
|
|
|
if (out_tlp_hdr1[seg]) begin
|
|
out_tlp_data[seg*INT_TLP_SEG_DATA_WIDTH +: INT_TLP_SEG_DATA_WIDTH] = seg_cc_hdr[63:0];
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out_tlp_strb[seg*INT_TLP_SEG_STRB_WIDTH +: INT_TLP_SEG_STRB_WIDTH] = 2'b11;
|
|
end else if (out_tlp_hdr2[seg]) begin
|
|
out_tlp_data[seg*INT_TLP_SEG_DATA_WIDTH +: 32] = seg_cc_hdr[95:64];
|
|
out_tlp_strb[seg*INT_TLP_SEG_STRB_WIDTH +: 1] = 1'b1;
|
|
end
|
|
|
|
out_tlp_valid[seg] = out_sel[seg];
|
|
out_tlp_sop[seg] = out_sop[seg];
|
|
out_tlp_eop[seg] = out_eop[seg];
|
|
|
|
if (out_sel[seg]) begin
|
|
out_shift_tlp_data_next = fifo_tlp_data[(out_sel_seg[seg]+1)*INT_TLP_SEG_DATA_WIDTH-32 +: 32];
|
|
out_shift_tlp_strb_next = fifo_tlp_strb[(out_sel_seg[seg]+1)*INT_TLP_SEG_STRB_WIDTH-1 +: 1];
|
|
end
|
|
end else begin
|
|
out_tlp_data[seg*INT_TLP_SEG_DATA_WIDTH +: INT_TLP_SEG_DATA_WIDTH] = out_shift_tlp_data_next;
|
|
out_tlp_strb[seg*INT_TLP_SEG_STRB_WIDTH +: INT_TLP_SEG_STRB_WIDTH] = out_shift_tlp_strb_next;
|
|
out_tlp_data[seg*INT_TLP_SEG_DATA_WIDTH+96 +: INT_TLP_SEG_DATA_WIDTH-96] = fifo_tlp_data[out_sel_seg[seg]*INT_TLP_SEG_DATA_WIDTH +: INT_TLP_SEG_DATA_WIDTH-96];
|
|
if (!out_tlp_split2[seg]) begin
|
|
out_tlp_strb[seg*INT_TLP_SEG_STRB_WIDTH+3 +: INT_TLP_SEG_STRB_WIDTH-3] = fifo_tlp_strb[out_sel_seg[seg]*INT_TLP_SEG_STRB_WIDTH +: INT_TLP_SEG_STRB_WIDTH-3];
|
|
end
|
|
|
|
if (out_tlp_hdr1[seg]) begin
|
|
out_tlp_data[seg*INT_TLP_SEG_DATA_WIDTH +: 96] = seg_cc_hdr;
|
|
out_tlp_strb[seg*INT_TLP_SEG_STRB_WIDTH +: 3] = 3'b111;
|
|
end
|
|
|
|
out_tlp_valid[seg] = out_sel[seg];
|
|
out_tlp_sop[seg] = out_sop[seg];
|
|
out_tlp_eop[seg] = out_eop[seg];
|
|
|
|
if (out_sel[seg]) begin
|
|
out_shift_tlp_data_next = fifo_tlp_data[(out_sel_seg[seg]+1)*INT_TLP_SEG_DATA_WIDTH-96 +: 96];
|
|
out_shift_tlp_strb_next = fifo_tlp_strb[(out_sel_seg[seg]+1)*INT_TLP_SEG_STRB_WIDTH-3 +: 3];
|
|
end
|
|
end
|
|
end
|
|
|
|
if (!m_axis_cc_tvalid || m_axis_cc_tready) begin
|
|
// remap header and sideband
|
|
m_axis_cc_tdata_next = out_tlp_data;
|
|
m_axis_cc_tkeep_next = 0;
|
|
m_axis_cc_tvalid_next = out_tlp_valid != 0;
|
|
m_axis_cc_tlast_next = !(CC_STRADDLE && AXIS_PCIE_DATA_WIDTH == 512) && (out_tlp_valid & out_tlp_eop);
|
|
m_axis_cc_tuser_next = 0;
|
|
|
|
for (seg = 0; seg < INT_TLP_SEG_COUNT; seg = seg + 1) begin
|
|
if (out_tlp_valid[seg]) begin
|
|
m_axis_cc_tkeep_next[seg*INT_TLP_SEG_STRB_WIDTH +: INT_TLP_SEG_STRB_WIDTH] = out_tlp_strb[seg*INT_TLP_SEG_STRB_WIDTH +: INT_TLP_SEG_STRB_WIDTH];
|
|
end
|
|
|
|
eop_index[seg*3 +: 3] = 0;
|
|
for (lane = 0; lane < INT_TLP_SEG_STRB_WIDTH; lane = lane + 1) begin
|
|
if (out_tlp_strb[seg*INT_TLP_SEG_STRB_WIDTH+lane]) begin
|
|
eop_index[seg*3 +: 3] = lane;
|
|
end
|
|
end
|
|
end
|
|
|
|
if (AXIS_PCIE_DATA_WIDTH == 512) begin
|
|
case (out_tlp_valid & out_tlp_sop)
|
|
2'b00: begin
|
|
m_axis_cc_tuser_next[1:0] = 2'b00; // is_sop
|
|
m_axis_cc_tuser_next[3:2] = 2'd0; // is_sop0_ptr
|
|
m_axis_cc_tuser_next[5:4] = 2'd0; // is_sop1_ptr
|
|
end
|
|
2'b01: begin
|
|
m_axis_cc_tuser_next[1:0] = 2'b01; // is_sop
|
|
m_axis_cc_tuser_next[3:2] = 2'd0; // is_sop0_ptr
|
|
m_axis_cc_tuser_next[5:4] = 2'd0; // is_sop1_ptr
|
|
end
|
|
2'b10: begin
|
|
m_axis_cc_tuser_next[1:0] = 2'b01; // is_sop
|
|
m_axis_cc_tuser_next[3:2] = 2'd2; // is_sop0_ptr
|
|
m_axis_cc_tuser_next[5:4] = 2'd0; // is_sop1_ptr
|
|
end
|
|
2'b11: begin
|
|
m_axis_cc_tuser_next[1:0] = 2'b11; // is_sop
|
|
m_axis_cc_tuser_next[3:2] = 2'd0; // is_sop0_ptr
|
|
m_axis_cc_tuser_next[5:4] = 2'd2; // is_sop1_ptr
|
|
end
|
|
endcase
|
|
case (out_tlp_valid & out_tlp_eop)
|
|
2'b00: begin
|
|
m_axis_cc_tuser_next[7:6] = 2'b00; // is_eop
|
|
m_axis_cc_tuser_next[11:8] = 4'd0; // is_eop0_ptr
|
|
m_axis_cc_tuser_next[15:12] = 4'd0; // is_eop1_ptr
|
|
end
|
|
2'b01: begin
|
|
m_axis_cc_tuser_next[7:6] = 2'b01; // is_eop
|
|
m_axis_cc_tuser_next[11:8] = eop_index[0*3 +: 3]; // is_eop0_ptr
|
|
m_axis_cc_tuser_next[15:12] = 4'd0; // is_eop1_ptr
|
|
end
|
|
2'b10: begin
|
|
m_axis_cc_tuser_next[7:6] = 2'b01; // is_eop
|
|
m_axis_cc_tuser_next[11:8] = 4'd8+eop_index[1*3 +: 3]; // is_eop0_ptr
|
|
m_axis_cc_tuser_next[15:12] = 4'd0; // is_eop1_ptr
|
|
end
|
|
2'b11: begin
|
|
m_axis_cc_tuser_next[7:6] = 2'b11; // is_eop
|
|
m_axis_cc_tuser_next[11:8] = eop_index[0*3 +: 3]; // is_eop0_ptr
|
|
m_axis_cc_tuser_next[15:12] = 4'd8+eop_index[1*3 +: 3]; // is_eop1_ptr
|
|
end
|
|
endcase
|
|
m_axis_cc_tuser_next[16] = 1'b0; // discontinue
|
|
m_axis_cc_tuser_next[80:17] = 64'd0; // parity
|
|
end else begin
|
|
m_axis_cc_tuser_next[1] = 1'b0; // discontinue
|
|
m_axis_cc_tuser_next[32:1] = 32'd0; // parity
|
|
end
|
|
end
|
|
end
|
|
|
|
integer i;
|
|
|
|
always @(posedge clk) begin
|
|
frame_reg <= frame_next;
|
|
tlp_hdr1_reg <= tlp_hdr1_next;
|
|
tlp_hdr2_reg <= tlp_hdr2_next;
|
|
tlp_split1_reg <= tlp_split1_next;
|
|
tlp_split2_reg <= tlp_split2_next;
|
|
|
|
out_shift_tlp_data_reg <= out_shift_tlp_data_next;
|
|
out_shift_tlp_strb_reg <= out_shift_tlp_strb_next;
|
|
|
|
m_axis_cc_tdata_reg <= m_axis_cc_tdata_next;
|
|
m_axis_cc_tkeep_reg <= m_axis_cc_tkeep_next;
|
|
m_axis_cc_tvalid_reg <= m_axis_cc_tvalid_next;
|
|
m_axis_cc_tlast_reg <= m_axis_cc_tlast_next;
|
|
m_axis_cc_tuser_reg <= m_axis_cc_tuser_next;
|
|
|
|
if (rst) begin
|
|
frame_reg <= 1'b0;
|
|
|
|
m_axis_cc_tvalid_reg <= 0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|