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250 lines
9.5 KiB
Verilog
250 lines
9.5 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI CDMA descriptor mux
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*/
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module axi_cdma_desc_mux #
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(
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parameter PORTS = 2,
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parameter AXI_ADDR_WIDTH = 16,
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parameter LEN_WIDTH = 20,
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parameter S_TAG_WIDTH = 8,
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parameter M_TAG_WIDTH = S_TAG_WIDTH+$clog2(PORTS),
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// arbitration type: "PRIORITY" or "ROUND_ROBIN"
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parameter ARB_TYPE = "PRIORITY",
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// LSB priority: "LOW", "HIGH"
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parameter LSB_PRIORITY = "HIGH"
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Descriptor output (to AXI CDMA core)
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*/
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output wire [AXI_ADDR_WIDTH-1:0] m_axis_desc_read_addr,
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output wire [AXI_ADDR_WIDTH-1:0] m_axis_desc_write_addr,
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output wire [LEN_WIDTH-1:0] m_axis_desc_len,
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output wire [M_TAG_WIDTH-1:0] m_axis_desc_tag,
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output wire m_axis_desc_valid,
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input wire m_axis_desc_ready,
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/*
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* Descriptor status input (from AXI CDMA core)
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*/
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input wire [M_TAG_WIDTH-1:0] s_axis_desc_status_tag,
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input wire s_axis_desc_status_valid,
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/*
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* Descriptor input
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*/
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input wire [PORTS*AXI_ADDR_WIDTH-1:0] s_axis_desc_read_addr,
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input wire [PORTS*AXI_ADDR_WIDTH-1:0] s_axis_desc_write_addr,
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input wire [PORTS*LEN_WIDTH-1:0] s_axis_desc_len,
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input wire [PORTS*S_TAG_WIDTH-1:0] s_axis_desc_tag,
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input wire [PORTS-1:0] s_axis_desc_valid,
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output wire [PORTS-1:0] s_axis_desc_ready,
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/*
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* Descriptor status output
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*/
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output wire [PORTS*S_TAG_WIDTH-1:0] m_axis_desc_status_tag,
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output wire [PORTS-1:0] m_axis_desc_status_valid
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);
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parameter CL_PORTS = $clog2(PORTS);
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// check configuration
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initial begin
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if (M_TAG_WIDTH < S_TAG_WIDTH+$clog2(PORTS)) begin
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$error("Error: M_TAG_WIDTH must be at least $clog2(PORTS) larger than S_TAG_WIDTH");
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$finish;
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end
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end
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// descriptor mux
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wire [PORTS-1:0] request;
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wire [PORTS-1:0] acknowledge;
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wire [PORTS-1:0] grant;
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wire grant_valid;
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wire [CL_PORTS-1:0] grant_encoded;
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// internal datapath
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reg [AXI_ADDR_WIDTH-1:0] m_axis_desc_read_addr_int;
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reg [AXI_ADDR_WIDTH-1:0] m_axis_desc_write_addr_int;
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reg [LEN_WIDTH-1:0] m_axis_desc_len_int;
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reg [M_TAG_WIDTH-1:0] m_axis_desc_tag_int;
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reg m_axis_desc_valid_int;
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reg m_axis_desc_ready_int_reg = 1'b0;
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wire m_axis_desc_ready_int_early;
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assign s_axis_desc_ready = (m_axis_desc_ready_int_reg && grant_valid) << grant_encoded;
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// mux for incoming packet
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wire [AXI_ADDR_WIDTH-1:0] current_s_desc_read_addr = s_axis_desc_read_addr[grant_encoded*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH];
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wire [AXI_ADDR_WIDTH-1:0] current_s_desc_write_addr = s_axis_desc_write_addr[grant_encoded*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH];
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wire [LEN_WIDTH-1:0] current_s_desc_len = s_axis_desc_len[grant_encoded*LEN_WIDTH +: LEN_WIDTH];
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wire [S_TAG_WIDTH-1:0] current_s_desc_tag = s_axis_desc_tag[grant_encoded*S_TAG_WIDTH +: S_TAG_WIDTH];
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wire current_s_desc_valid = s_axis_desc_valid[grant_encoded];
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wire current_s_desc_ready = s_axis_desc_ready[grant_encoded];
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// arbiter instance
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arbiter #(
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.PORTS(PORTS),
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.TYPE(ARB_TYPE),
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.BLOCK("ACKNOWLEDGE"),
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.LSB_PRIORITY(LSB_PRIORITY)
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.request(request),
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.acknowledge(acknowledge),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_encoded(grant_encoded)
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);
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assign request = s_axis_desc_valid & ~grant;
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assign acknowledge = grant & s_axis_desc_valid & s_axis_desc_ready;
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always @* begin
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m_axis_desc_read_addr_int = current_s_desc_read_addr;
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m_axis_desc_write_addr_int = current_s_desc_write_addr;
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m_axis_desc_len_int = current_s_desc_len;
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m_axis_desc_tag_int = {grant_encoded, current_s_desc_tag};
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m_axis_desc_valid_int = current_s_desc_valid && m_axis_desc_ready_int_reg && grant_valid;
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end
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// output datapath logic
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reg [AXI_ADDR_WIDTH-1:0] m_axis_desc_read_addr_reg = {AXI_ADDR_WIDTH{1'b0}};
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reg [AXI_ADDR_WIDTH-1:0] m_axis_desc_write_addr_reg = {AXI_ADDR_WIDTH{1'b0}};
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reg [LEN_WIDTH-1:0] m_axis_desc_len_reg = {LEN_WIDTH{1'b0}};
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reg [M_TAG_WIDTH-1:0] m_axis_desc_tag_reg = {M_TAG_WIDTH{1'b0}};
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reg m_axis_desc_valid_reg = 1'b0, m_axis_desc_valid_next;
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reg [AXI_ADDR_WIDTH-1:0] temp_m_axis_desc_read_addr_reg = {AXI_ADDR_WIDTH{1'b0}};
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reg [AXI_ADDR_WIDTH-1:0] temp_m_axis_desc_write_addr_reg = {AXI_ADDR_WIDTH{1'b0}};
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reg [LEN_WIDTH-1:0] temp_m_axis_desc_len_reg = {LEN_WIDTH{1'b0}};
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reg [M_TAG_WIDTH-1:0] temp_m_axis_desc_tag_reg = {M_TAG_WIDTH{1'b0}};
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reg temp_m_axis_desc_valid_reg = 1'b0, temp_m_axis_desc_valid_next;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign m_axis_desc_read_addr = m_axis_desc_read_addr_reg;
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assign m_axis_desc_write_addr = m_axis_desc_write_addr_reg;
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assign m_axis_desc_len = m_axis_desc_len_reg;
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assign m_axis_desc_tag = m_axis_desc_tag_reg;
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assign m_axis_desc_valid = m_axis_desc_valid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign m_axis_desc_ready_int_early = m_axis_desc_ready || (!temp_m_axis_desc_valid_reg && (!m_axis_desc_valid_reg || !m_axis_desc_valid_int));
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always @* begin
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// transfer sink ready state to source
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m_axis_desc_valid_next = m_axis_desc_valid_reg;
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temp_m_axis_desc_valid_next = temp_m_axis_desc_valid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (m_axis_desc_ready_int_reg) begin
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// input is ready
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if (m_axis_desc_ready || !m_axis_desc_valid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_desc_valid_next = m_axis_desc_valid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_desc_valid_next = m_axis_desc_valid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis_desc_ready) begin
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// input is not ready, but output is ready
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m_axis_desc_valid_next = temp_m_axis_desc_valid_reg;
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temp_m_axis_desc_valid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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m_axis_desc_valid_reg <= 1'b0;
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m_axis_desc_ready_int_reg <= 1'b0;
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temp_m_axis_desc_valid_reg <= 1'b0;
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end else begin
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m_axis_desc_valid_reg <= m_axis_desc_valid_next;
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m_axis_desc_ready_int_reg <= m_axis_desc_ready_int_early;
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temp_m_axis_desc_valid_reg <= temp_m_axis_desc_valid_next;
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end
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// datapath
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if (store_axis_int_to_output) begin
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m_axis_desc_read_addr_reg <= m_axis_desc_read_addr_int;
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m_axis_desc_write_addr_reg <= m_axis_desc_write_addr_int;
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m_axis_desc_len_reg <= m_axis_desc_len_int;
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m_axis_desc_tag_reg <= m_axis_desc_tag_int;
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end else if (store_axis_temp_to_output) begin
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m_axis_desc_read_addr_reg <= temp_m_axis_desc_read_addr_reg;
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m_axis_desc_write_addr_reg <= temp_m_axis_desc_write_addr_reg;
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m_axis_desc_len_reg <= temp_m_axis_desc_len_reg;
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m_axis_desc_tag_reg <= temp_m_axis_desc_tag_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_m_axis_desc_read_addr_reg <= m_axis_desc_read_addr_int;
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temp_m_axis_desc_write_addr_reg <= m_axis_desc_write_addr_int;
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temp_m_axis_desc_len_reg <= m_axis_desc_len_int;
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temp_m_axis_desc_tag_reg <= m_axis_desc_tag_int;
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end
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end
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// descriptor status demux
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reg [S_TAG_WIDTH-1:0] m_axis_desc_status_tag_reg = {S_TAG_WIDTH{1'b0}};
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reg [PORTS-1:0] m_axis_desc_status_valid_reg = {PORTS{1'b0}};
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assign m_axis_desc_status_tag = {PORTS{m_axis_desc_status_tag_reg}};
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assign m_axis_desc_status_valid = m_axis_desc_status_valid_reg;
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always @(posedge clk) begin
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if (rst) begin
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m_axis_desc_status_valid_reg <= {PORTS{1'b0}};
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end else begin
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m_axis_desc_status_valid_reg <= s_axis_desc_status_valid << (PORTS > 1 ? s_axis_desc_status_tag[S_TAG_WIDTH+CL_PORTS-1:S_TAG_WIDTH] : 0);
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end
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m_axis_desc_status_tag_reg <= s_axis_desc_status_tag;
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end
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endmodule
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