Alex Forencich 74f32c6a59 Add missing PHY instance ports

2021-11-02 20:28:26 -07:00

..

debounce_switch.v

Add default_nettype none and resetall directives

2021-10-20 17:29:12 -07:00

eth_xcvr_phy_wrapper.v

Add default_nettype none and resetall directives

2021-10-20 17:29:12 -07:00

fpga_core.v

Add default_nettype none and resetall directives

2021-10-20 17:29:12 -07:00

fpga.v

Add missing PHY instance ports

2021-11-02 20:28:26 -07:00

i2c_master.v

Add default_nettype none and resetall directives

2021-10-20 17:29:12 -07:00

si5341_i2c_init.py

Add default_nettype none and resetall directives

2021-10-20 17:29:12 -07:00

si5341_i2c_init.v

Add default_nettype none and resetall directives

2021-10-20 17:29:12 -07:00

Si5341-RevD-fpga-161-osc-Registers.txt

Add HTG-9200 10G example design

2021-07-08 11:58:04 -07:00

sync_signal.v

Add default_nettype none and resetall directives

2021-10-20 17:29:12 -07:00