mirror of
https://github.com/corundum/corundum.git
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166 lines
4.6 KiB
Python
166 lines
4.6 KiB
Python
#!/usr/bin/env python
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"""
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import logging
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import os
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Timer
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from cocotbext.eth import PtpClock
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
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self.ptp_clock = PtpClock(
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ts_96=dut.input_ts_96,
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ts_step=dut.input_ts_step,
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clock=dut.clk,
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reset=dut.rst,
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period_ns=6.4
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)
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dut.enable.setimmediatevalue(0)
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dut.input_start.setimmediatevalue(0)
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dut.input_start_valid.setimmediatevalue(0)
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dut.input_period.setimmediatevalue(0)
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dut.input_period_valid.setimmediatevalue(0)
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dut.input_width.setimmediatevalue(0)
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dut.input_width_valid.setimmediatevalue(0)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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@cocotb.test()
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async def run_test(dut):
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tb = TB(dut)
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await tb.reset()
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dut.enable.value = 1
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await RisingEdge(dut.clk)
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dut.input_start.value = 100 << 16
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dut.input_start_valid.value = 1
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dut.input_period.value = 100 << 16
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dut.input_period_valid.value = 1
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dut.input_width.value = 50 << 16
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dut.input_width_valid.value = 1
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await RisingEdge(dut.clk)
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dut.input_start_valid.value = 0
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dut.input_period_valid.value = 0
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dut.input_width_valid.value = 0
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await Timer(10000, 'ns')
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await RisingEdge(dut.clk)
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dut.input_start.value = 0 << 16
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dut.input_start_valid.value = 1
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dut.input_period.value = 100 << 16
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dut.input_period_valid.value = 1
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dut.input_width.value = 50 << 16
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dut.input_width_valid.value = 1
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await RisingEdge(dut.clk)
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dut.input_start_valid.value = 0
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dut.input_period_valid.value = 0
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dut.input_width_valid.value = 0
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await Timer(10000, 'ns')
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
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axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
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def test_ptp_perout(request):
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dut = "ptp_perout"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(rtl_dir, f"{dut}.v"),
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]
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parameters = {}
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parameters['FNS_ENABLE'] = 1
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parameters['OUT_START_S'] = 0
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parameters['OUT_START_NS'] = 0
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parameters['OUT_START_FNS'] = 0x0000
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parameters['OUT_PERIOD_S'] = 1
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parameters['OUT_PERIOD_NS'] = 0
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parameters['OUT_PERIOD_FNS'] = 0x0000
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parameters['OUT_WIDTH_S'] = 0
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parameters['OUT_WIDTH_NS'] = 1000
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parameters['OUT_WIDTH_FNS'] = 0x0000
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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