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corundum/fpga/common/rtl
History
Alex Forencich 3003b3228d Fix backpressure bug in TX checksum module
2020-12-12 21:51:54 -08:00
..
cmac_pad.v
Fix cmac_pad frame truncation bug
2020-04-22 23:23:34 -07:00
cpl_op_mux.v
Add completion op mux module
2019-09-23 14:47:09 -07:00
cpl_queue_manager.v
Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH
2020-04-20 18:43:26 -07:00
cpl_write.v
Update DMA RAM instances
2020-09-25 21:51:31 -07:00
desc_fetch.v
Update DMA RAM instances
2020-09-25 21:51:31 -07:00
desc_op_mux.v
Add descriptor op mux module
2019-09-23 14:47:00 -07:00
event_mux.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
mqnic_interface.v
Rename port and interface modules
2020-11-26 15:05:59 -08:00
mqnic_port.v
Rename port and interface modules
2020-11-26 15:05:59 -08:00
queue_manager.v
Add log desc block size field to queue manager
2020-04-20 20:45:10 -07:00
rx_checksum.v
Parametrize checksum offload
2019-11-13 23:49:50 -08:00
rx_engine.v
Limit RX DMA size to configured MTU size
2020-08-25 18:48:17 -07:00
rx_hash.v
Add rx_hash module and testbenches
2019-12-05 13:47:07 -08:00
tdma_ber_ch.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_ber.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_scheduler.v
Update TDMA scheduler to generate status signals and avoid producing runt outputs
2019-11-05 16:55:19 -08:00
tx_checksum.v
Fix backpressure bug in TX checksum module
2020-12-12 21:51:54 -08:00
tx_engine.v
Rewrite TX buffer management
2020-05-01 14:29:52 -07:00
tx_scheduler_ctrl_tdma.v
Add tx_scheduler_ctrl_tdma module
2019-11-05 18:24:22 -08:00
tx_scheduler_rr.v
Remove unused table fields
2019-12-30 22:02:22 -08:00