mirror of
https://github.com/corundum/corundum.git
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88 lines
5.1 KiB
Tcl
88 lines
5.1 KiB
Tcl
# Copyright (c) 2019 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# PTP timestamp capture module
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foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NAME == ptp_clock_cdc)}] {
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puts "Inserting timing constraints for ptp_clock_cdc instance $inst"
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# get clock periods
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set input_clk [get_clocks -of_objects [get_pins $inst/wr_ptr_reg_reg[0]/C]]
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set output_clk [get_clocks -of_objects [get_pins $inst/rd_ptr_reg_reg[0]/C]]
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set input_clk_period [get_property -min PERIOD $input_clk]
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set output_clk_period [get_property -min PERIOD $output_clk]
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# pointer synchronization
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set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/(wr|rd)_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
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set_max_delay -from [get_cells "$inst/rd_ptr_reg_reg[*] $inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $inst/rd_ptr_gray_sync1_reg_reg[*]] -datapath_only $output_clk_period
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set_bus_skew -from [get_cells "$inst/rd_ptr_reg_reg[*] $inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $inst/rd_ptr_gray_sync1_reg_reg[*]] $input_clk_period
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set_max_delay -from [get_cells "$inst/wr_ptr_reg_reg[*] $inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells $inst/wr_ptr_gray_sync1_reg_reg[*]] -datapath_only $input_clk_period
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set_bus_skew -from [get_cells "$inst/wr_ptr_reg_reg[*] $inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells $inst/wr_ptr_gray_sync1_reg_reg[*]] $output_clk_period
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# output register (needed for distributed RAM sync write/async read)
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set output_reg_ffs [get_cells -quiet "$inst/mem_read_data_reg_reg[*]"]
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if {[llength $output_reg_ffs]} {
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set_false_path -from $input_clk -to $output_reg_ffs
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}
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# pointer synchronization (depth measurement)
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set sync_ffs [get_cells -quiet -hier -regexp ".*/rd_ptr_gray_sample_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set src_clk [get_clocks -of_objects [get_pins $inst/rd_ptr_gray_reg_reg[0]/C]]
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set dest_clk [get_clocks -of_objects [get_pins $inst/rd_ptr_gray_sample_sync1_reg_reg[0]/C]]
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set_max_delay -from [get_cells "$inst/rd_ptr_reg_reg[*] $inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $inst/rd_ptr_gray_sample_sync1_reg_reg[*]] -datapath_only [get_property -min PERIOD $src_clk]
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set_bus_skew -from [get_cells "$inst/rd_ptr_reg_reg[*] $inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $inst/rd_ptr_gray_sample_sync1_reg_reg[*]] [get_property -min PERIOD $dest_clk]
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}
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set sync_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_gray_sample_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set src_clk [get_clocks -of_objects [get_pins $inst/wr_ptr_gray_reg_reg[0]/C]]
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set dest_clk [get_clocks -of_objects [get_pins $inst/wr_ptr_gray_sample_sync1_reg_reg[0]/C]]
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set_max_delay -from [get_cells "$inst/wr_ptr_reg_reg[*] $inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells $inst/wr_ptr_gray_sample_sync1_reg_reg[*]] -datapath_only [get_property -min PERIOD $src_clk]
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set_bus_skew -from [get_cells "$inst/wr_ptr_reg_reg[*] $inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells $inst/wr_ptr_gray_sample_sync1_reg_reg[*]] [get_property -min PERIOD $dest_clk]
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}
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# sample update sync
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set sync_ffs [get_cells -quiet -hier -regexp ".*/sample_update_sync\[123\]_reg_reg" -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set src_clk [get_clocks -of_objects [get_pins $inst/sample_update_reg_reg/C]]
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set dest_clk [get_clocks -of_objects [get_pins $inst/sample_update_sync1_reg_reg/C]]
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set_max_delay -from [get_cells $inst/sample_update_reg_reg] -to [get_cells $inst/sample_update_sync1_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
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set_max_delay -from [get_cells "$inst/sample_avg_reg_reg[*]"] -to [get_cells $inst/sample_avg_sync_reg_reg[*]] -datapath_only [get_property -min PERIOD $src_clk]
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set_bus_skew -from [get_cells "$inst/sample_avg_reg_reg[*]"] -to [get_cells $inst/sample_avg_sync_reg_reg[*]] [get_property -min PERIOD $dest_clk]
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}
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}
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