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289 lines
10 KiB
Verilog
289 lines
10 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 RAM write interface
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*/
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module axi_ram_wr_if #
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(
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// Width of data bus in bits
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parameter DATA_WIDTH = 32,
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// Width of address bus in bits
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parameter ADDR_WIDTH = 16,
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// Width of wstrb (width of data bus in words)
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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// Width of ID signal
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parameter ID_WIDTH = 8,
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// Propagate awuser signal
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parameter AWUSER_ENABLE = 0,
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// Width of awuser signal
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parameter AWUSER_WIDTH = 1,
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// Propagate wuser signal
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parameter WUSER_ENABLE = 0,
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// Width of wuser signal
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parameter WUSER_WIDTH = 1,
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// Propagate buser signal
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parameter BUSER_ENABLE = 0,
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// Width of buser signal
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parameter BUSER_WIDTH = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interface
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*/
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input wire [ID_WIDTH-1:0] s_axi_awid,
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input wire [ADDR_WIDTH-1:0] s_axi_awaddr,
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input wire [7:0] s_axi_awlen,
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input wire [2:0] s_axi_awsize,
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input wire [1:0] s_axi_awburst,
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input wire s_axi_awlock,
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input wire [3:0] s_axi_awcache,
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input wire [2:0] s_axi_awprot,
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input wire [3:0] s_axi_awqos,
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input wire [3:0] s_axi_awregion,
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input wire [AWUSER_WIDTH-1:0] s_axi_awuser,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [DATA_WIDTH-1:0] s_axi_wdata,
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input wire [STRB_WIDTH-1:0] s_axi_wstrb,
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input wire s_axi_wlast,
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input wire [WUSER_WIDTH-1:0] s_axi_wuser,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [ID_WIDTH-1:0] s_axi_bid,
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output wire [1:0] s_axi_bresp,
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output wire [BUSER_WIDTH-1:0] s_axi_buser,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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/*
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* RAM interface
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*/
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output wire [ID_WIDTH-1:0] ram_wr_cmd_id,
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output wire [ADDR_WIDTH-1:0] ram_wr_cmd_addr,
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output wire ram_wr_cmd_lock,
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output wire [3:0] ram_wr_cmd_cache,
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output wire [2:0] ram_wr_cmd_prot,
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output wire [3:0] ram_wr_cmd_qos,
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output wire [3:0] ram_wr_cmd_region,
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output wire [AWUSER_WIDTH-1:0] ram_wr_cmd_auser,
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output wire [DATA_WIDTH-1:0] ram_wr_cmd_data,
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output wire [STRB_WIDTH-1:0] ram_wr_cmd_strb,
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output wire [WUSER_WIDTH-1:0] ram_wr_cmd_user,
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output wire ram_wr_cmd_en,
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output wire ram_wr_cmd_last,
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input wire ram_wr_cmd_ready
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);
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parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH);
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parameter WORD_WIDTH = STRB_WIDTH;
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parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
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// bus width assertions
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initial begin
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if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
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$error("Error: AXI data width not evenly divisble (instance %m)");
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$finish;
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end
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if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
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$error("Error: AXI word width must be even power of two (instance %m)");
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$finish;
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end
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end
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_BURST = 2'd1,
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STATE_RESP = 2'd2;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg [ID_WIDTH-1:0] write_id_reg = {ID_WIDTH{1'b0}}, write_id_next;
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reg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next;
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reg write_lock_reg = 1'b0, write_lock_next;
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reg [3:0] write_cache_reg = 4'd0, write_cache_next;
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reg [2:0] write_prot_reg = 3'd0, write_prot_next;
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reg [3:0] write_qos_reg = 4'd0, write_qos_next;
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reg [3:0] write_region_reg = 4'd0, write_region_next;
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reg [AWUSER_WIDTH-1:0] write_awuser_reg = {AWUSER_WIDTH{1'b0}}, write_awuser_next;
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reg write_addr_valid_reg = 1'b0, write_addr_valid_next;
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reg write_last_reg = 1'b0, write_last_next;
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reg [7:0] write_count_reg = 8'd0, write_count_next;
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reg [2:0] write_size_reg = 3'd0, write_size_next;
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reg [1:0] write_burst_reg = 2'd0, write_burst_next;
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reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
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reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}, s_axi_bid_next;
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reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
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assign s_axi_awready = s_axi_awready_reg;
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assign s_axi_wready = write_addr_valid_reg && ram_wr_cmd_ready;
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assign s_axi_bid = s_axi_bid_reg;
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assign s_axi_bresp = 2'b00;
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assign s_axi_buser = {BUSER_WIDTH{1'b0}};
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assign s_axi_bvalid = s_axi_bvalid_reg;
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assign ram_wr_cmd_id = write_id_reg;
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assign ram_wr_cmd_addr = write_addr_reg;
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assign ram_wr_cmd_lock = write_lock_reg;
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assign ram_wr_cmd_cache = write_cache_reg;
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assign ram_wr_cmd_prot = write_prot_reg;
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assign ram_wr_cmd_qos = write_qos_reg;
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assign ram_wr_cmd_region = write_region_reg;
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assign ram_wr_cmd_auser = AWUSER_ENABLE ? write_awuser_reg : {AWUSER_WIDTH{1'b0}};
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assign ram_wr_cmd_data = s_axi_wdata;
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assign ram_wr_cmd_strb = s_axi_wstrb;
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assign ram_wr_cmd_user = WUSER_ENABLE ? s_axi_wuser : {WUSER_WIDTH{1'b0}};
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assign ram_wr_cmd_en = write_addr_valid_reg && s_axi_wvalid;
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assign ram_wr_cmd_last = write_last_reg;
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always @* begin
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state_next = STATE_IDLE;
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write_id_next = write_id_reg;
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write_addr_next = write_addr_reg;
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write_lock_next = write_lock_reg;
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write_cache_next = write_cache_reg;
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write_prot_next = write_prot_reg;
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write_qos_next = write_qos_reg;
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write_region_next = write_region_reg;
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write_awuser_next = write_awuser_reg;
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write_addr_valid_next = write_addr_valid_reg;
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write_last_next = write_last_reg;
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write_count_next = write_count_reg;
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write_size_next = write_size_reg;
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write_burst_next = write_burst_reg;
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s_axi_awready_next = 1'b0;
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s_axi_bid_next = s_axi_bid_reg;
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s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;
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case (state_reg)
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STATE_IDLE: begin
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s_axi_awready_next = 1'b1;
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if (s_axi_awready && s_axi_awvalid) begin
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write_id_next = s_axi_awid;
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write_addr_next = s_axi_awaddr;
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write_lock_next = s_axi_awlock;
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write_cache_next = s_axi_awcache;
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write_prot_next = s_axi_awprot;
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write_qos_next = s_axi_awqos;
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write_region_next = s_axi_awregion;
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write_awuser_next = s_axi_awuser;
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write_count_next = s_axi_awlen;
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write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH);
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write_burst_next = s_axi_awburst;
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write_addr_valid_next = 1'b1;
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s_axi_awready_next = 1'b0;
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if (s_axi_awlen > 0) begin
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write_last_next = 1'b0;
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end else begin
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write_last_next = 1'b1;
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end
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state_next = STATE_BURST;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_BURST: begin
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if (s_axi_wready && s_axi_wvalid) begin
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if (write_burst_reg != 2'b00) begin
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write_addr_next = write_addr_reg + (1 << write_size_reg);
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end
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write_count_next = write_count_reg - 1;
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write_last_next = write_count_next == 0;
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if (write_count_reg > 0) begin
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write_addr_valid_next = 1'b1;
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state_next = STATE_BURST;
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end else begin
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write_addr_valid_next = 1'b0;
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if (s_axi_bready || !s_axi_bvalid) begin
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s_axi_bid_next = write_id_reg;
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s_axi_bvalid_next = 1'b1;
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s_axi_awready_next = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_RESP;
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end
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end
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end else begin
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state_next = STATE_BURST;
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end
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end
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STATE_RESP: begin
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if (s_axi_bready || !s_axi_bvalid) begin
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s_axi_bid_next = write_id_reg;
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s_axi_bvalid_next = 1'b1;
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s_axi_awready_next = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_RESP;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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state_reg <= state_next;
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write_id_reg <= write_id_next;
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write_addr_reg <= write_addr_next;
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write_lock_reg <= write_lock_next;
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write_cache_reg <= write_cache_next;
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write_prot_reg <= write_prot_next;
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write_qos_reg <= write_qos_next;
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write_region_reg <= write_region_next;
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write_awuser_reg <= write_awuser_next;
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write_addr_valid_reg <= write_addr_valid_next;
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write_last_reg <= write_last_next;
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write_count_reg <= write_count_next;
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write_size_reg <= write_size_next;
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write_burst_reg <= write_burst_next;
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s_axi_awready_reg <= s_axi_awready_next;
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s_axi_bid_reg <= s_axi_bid_next;
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s_axi_bvalid_reg <= s_axi_bvalid_next;
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if (rst) begin
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state_reg <= STATE_IDLE;
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write_addr_valid_reg <= 1'b0;
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s_axi_awready_reg <= 1'b0;
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s_axi_bvalid_reg <= 1'b0;
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end
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end
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endmodule
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