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233 lines
7.0 KiB
Python
Executable File
233 lines
7.0 KiB
Python
Executable File
#!/usr/bin/env python2
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"""
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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from Queue import Queue
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import axis_ep
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import ll_ep
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module = 'axis_ll_bridge'
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("test_%s.v" % module)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
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def dut_axis_ll_bridge(clk,
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rst,
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current_test,
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axis_tdata,
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axis_tvalid,
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axis_tready,
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axis_tlast,
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ll_data_out,
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ll_sof_out_n,
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ll_eof_out_n,
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ll_src_rdy_out_n,
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ll_dst_rdy_in_n):
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if os.system(build_cmd):
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raise Exception("Error running build command")
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return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
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clk=clk,
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rst=rst,
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current_test=current_test,
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axis_tdata=axis_tdata,
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axis_tvalid=axis_tvalid,
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axis_tready=axis_tready,
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axis_tlast=axis_tlast,
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ll_data_out=ll_data_out,
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ll_sof_out_n=ll_sof_out_n,
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ll_eof_out_n=ll_eof_out_n,
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ll_src_rdy_out_n=ll_src_rdy_out_n,
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ll_dst_rdy_in_n=ll_dst_rdy_in_n)
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def bench():
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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axis_tdata = Signal(intbv(0)[8:])
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axis_tvalid = Signal(bool(0))
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axis_tlast = Signal(bool(0))
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ll_dst_rdy_in_n = Signal(bool(1))
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# Outputs
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ll_data_out = Signal(intbv(0)[8:])
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ll_sof_out_n = Signal(bool(1))
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ll_eof_out_n = Signal(bool(1))
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ll_src_rdy_out_n = Signal(bool(1))
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axis_tready = Signal(bool(0))
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# sources and sinks
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source_queue = Queue()
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source_pause = Signal(bool(0))
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sink_queue = Queue()
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sink_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource(clk,
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rst,
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tdata=axis_tdata,
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tvalid=axis_tvalid,
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tready=axis_tready,
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tlast=axis_tlast,
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fifo=source_queue,
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pause=source_pause,
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name='source')
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sink = ll_ep.LocalLinkSink(clk,
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rst,
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data_in=ll_data_out,
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sof_in_n=ll_sof_out_n,
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eof_in_n=ll_eof_out_n,
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src_rdy_in_n=ll_src_rdy_out_n,
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dst_rdy_out_n=ll_dst_rdy_in_n,
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fifo=sink_queue,
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pause=sink_pause,
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name='sink')
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# DUT
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dut = dut_axis_ll_bridge(clk,
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rst,
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current_test,
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axis_tdata,
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axis_tvalid,
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axis_tready,
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axis_tlast,
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ll_data_out,
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ll_sof_out_n,
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ll_eof_out_n,
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ll_src_rdy_out_n,
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ll_dst_rdy_in_n)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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print("test 1: test packet")
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current_test.next = 1
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source_queue.put(bytearray('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'))
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yield clk.posedge
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yield ll_eof_out_n.negedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert bytearray(rx_frame) == ('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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yield delay(100)
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yield clk.posedge
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print("test 2: test packet with pauses")
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current_test.next = 2
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source_queue.put(bytearray('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'))
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yield clk.posedge
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yield delay(64)
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yield clk.posedge
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source_pause.next = True
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yield delay(32)
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yield clk.posedge
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source_pause.next = False
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yield delay(64)
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yield clk.posedge
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sink_pause.next = True
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yield delay(32)
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yield clk.posedge
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sink_pause.next = False
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yield ll_eof_out_n.negedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert bytearray(rx_frame) == ('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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yield delay(100)
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raise StopSimulation
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return dut, source, sink, clkgen, check
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def test_bench():
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os.chdir(os.path.dirname(os.path.abspath(__file__)))
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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