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264 lines
8.4 KiB
Verilog
264 lines
8.4 KiB
Verilog
/*
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Copyright 2021, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PTP hardware clock
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*/
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module mqnic_ptp #
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(
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parameter PTP_CLK_PERIOD_NS_NUM = 4,
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parameter PTP_CLK_PERIOD_NS_DENOM = 1,
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parameter PTP_CLOCK_PIPELINE = 0,
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parameter PTP_CLOCK_CDC_PIPELINE = 0,
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parameter PTP_USE_SAMPLE_CLOCK = 0,
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parameter PTP_PEROUT_ENABLE = 0,
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parameter PTP_PEROUT_COUNT = 1,
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parameter REG_ADDR_WIDTH = 7+(PTP_PEROUT_ENABLE ? $clog2((PTP_PEROUT_COUNT+1)/2) + 1 : 0),
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parameter REG_DATA_WIDTH = 32,
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parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
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parameter RB_BASE_ADDR = 0,
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parameter RB_NEXT_PTR = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Register interface
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*/
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input wire [REG_ADDR_WIDTH-1:0] reg_wr_addr,
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input wire [REG_DATA_WIDTH-1:0] reg_wr_data,
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input wire [REG_STRB_WIDTH-1:0] reg_wr_strb,
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input wire reg_wr_en,
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output wire reg_wr_wait,
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output wire reg_wr_ack,
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input wire [REG_ADDR_WIDTH-1:0] reg_rd_addr,
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input wire reg_rd_en,
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output wire [REG_DATA_WIDTH-1:0] reg_rd_data,
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output wire reg_rd_wait,
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output wire reg_rd_ack,
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/*
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* PTP clock
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*/
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input wire ptp_clk,
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input wire ptp_rst,
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input wire ptp_sample_clk,
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output wire ptp_pps,
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output wire ptp_pps_str,
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output wire [95:0] ptp_ts_96,
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output wire ptp_ts_step,
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output wire ptp_sync_pps,
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output wire [95:0] ptp_sync_ts_96,
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output wire ptp_sync_ts_step,
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output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
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output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
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output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse
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);
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// bus width assertions
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initial begin
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if (REG_DATA_WIDTH != 32) begin
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$error("Error: Register interface width must be 32 (instance %m)");
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$finish;
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end
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if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin
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$error("Error: Register interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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if (REG_ADDR_WIDTH < 7+(PTP_PEROUT_ENABLE ? $clog2((PTP_PEROUT_COUNT+1)/2) + 1 : 0)) begin
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$error("Error: Register address width too narrow (instance %m)");
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$finish;
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end
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end
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wire clock_reg_wr_wait;
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wire clock_reg_wr_ack;
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wire [REG_DATA_WIDTH-1:0] clock_reg_rd_data;
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wire clock_reg_rd_wait;
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wire clock_reg_rd_ack;
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wire perout_reg_wr_wait[PTP_PEROUT_COUNT-1:0];
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wire perout_reg_wr_ack[PTP_PEROUT_COUNT-1:0];
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wire [REG_DATA_WIDTH-1:0] perout_reg_rd_data[PTP_PEROUT_COUNT-1:0];
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wire perout_reg_rd_wait[PTP_PEROUT_COUNT-1:0];
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wire perout_reg_rd_ack[PTP_PEROUT_COUNT-1:0];
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reg reg_wr_wait_cmb;
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reg reg_wr_ack_cmb;
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reg [REG_DATA_WIDTH-1:0] reg_rd_data_cmb;
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reg reg_rd_wait_cmb;
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reg reg_rd_ack_cmb;
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assign reg_wr_wait = reg_wr_wait_cmb;
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assign reg_wr_ack = reg_wr_ack_cmb;
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assign reg_rd_data = reg_rd_data_cmb;
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assign reg_rd_wait = reg_rd_wait_cmb;
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assign reg_rd_ack = reg_rd_ack_cmb;
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integer k;
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always @* begin
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reg_wr_wait_cmb = clock_reg_wr_wait;
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reg_wr_ack_cmb = clock_reg_wr_ack;
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reg_rd_data_cmb = clock_reg_rd_data;
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reg_rd_wait_cmb = clock_reg_rd_wait;
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reg_rd_ack_cmb = clock_reg_rd_ack;
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if (PTP_PEROUT_ENABLE) begin
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for (k = 0; k < PTP_PEROUT_COUNT; k = k + 1) begin
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reg_wr_wait_cmb = reg_wr_wait_cmb | perout_reg_wr_wait[k];
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reg_wr_ack_cmb = reg_wr_ack_cmb | perout_reg_wr_ack[k];
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reg_rd_data_cmb = reg_rd_data_cmb | perout_reg_rd_data[k];
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reg_rd_wait_cmb = reg_rd_wait_cmb | perout_reg_rd_wait[k];
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reg_rd_ack_cmb = reg_rd_ack_cmb | perout_reg_rd_ack[k];
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end
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end
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end
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mqnic_ptp_clock #(
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.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
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.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
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.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
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.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
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.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
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.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
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.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
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.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
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.REG_DATA_WIDTH(REG_DATA_WIDTH),
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.REG_STRB_WIDTH(REG_STRB_WIDTH),
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.RB_BASE_ADDR(RB_BASE_ADDR),
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.RB_NEXT_PTR(PTP_PEROUT_ENABLE ? RB_BASE_ADDR + 32'h80 : RB_NEXT_PTR)
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)
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ptp_clock_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Register interface
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*/
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.reg_wr_addr(reg_wr_addr),
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.reg_wr_data(reg_wr_data),
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.reg_wr_strb(reg_wr_strb),
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.reg_wr_en(reg_wr_en),
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.reg_wr_wait(clock_reg_wr_wait),
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.reg_wr_ack(clock_reg_wr_ack),
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.reg_rd_addr(reg_rd_addr),
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.reg_rd_en(reg_rd_en),
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.reg_rd_data(clock_reg_rd_data),
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.reg_rd_wait(clock_reg_rd_wait),
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.reg_rd_ack(clock_reg_rd_ack),
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/*
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* PTP clock
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*/
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.ptp_clk(ptp_clk),
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.ptp_rst(ptp_rst),
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.ptp_sample_clk(ptp_sample_clk),
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.ptp_pps(ptp_pps),
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.ptp_pps_str(ptp_pps_str),
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.ptp_ts_96(ptp_ts_96),
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.ptp_ts_step(ptp_ts_step),
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.ptp_sync_pps(ptp_sync_pps),
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.ptp_sync_ts_96(ptp_sync_ts_96),
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.ptp_sync_ts_step(ptp_sync_ts_step)
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);
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generate
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genvar n;
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if (PTP_PEROUT_ENABLE) begin
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for (n = 0; n < PTP_PEROUT_COUNT; n = n + 1) begin : perout
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mqnic_ptp_perout #(
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.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
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.REG_DATA_WIDTH(REG_DATA_WIDTH),
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.REG_STRB_WIDTH(REG_STRB_WIDTH),
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.RB_BASE_ADDR(RB_BASE_ADDR + 32'h80 + 32'h40*n),
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.RB_NEXT_PTR(n < PTP_PEROUT_COUNT-1 ? RB_BASE_ADDR + 32'h80 + 32'h40*(n+1) : RB_NEXT_PTR)
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)
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ptp_perout_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Register interface
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*/
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.reg_wr_addr(reg_wr_addr),
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.reg_wr_data(reg_wr_data),
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.reg_wr_strb(reg_wr_strb),
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.reg_wr_en(reg_wr_en),
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.reg_wr_wait(perout_reg_wr_wait[n]),
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.reg_wr_ack(perout_reg_wr_ack[n]),
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.reg_rd_addr(reg_rd_addr),
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.reg_rd_en(reg_rd_en),
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.reg_rd_data(perout_reg_rd_data[n]),
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.reg_rd_wait(perout_reg_rd_wait[n]),
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.reg_rd_ack(perout_reg_rd_ack[n]),
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/*
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* PTP clock
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*/
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.ptp_ts_96(ptp_sync_ts_96),
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.ptp_ts_step(ptp_sync_ts_step),
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.ptp_perout_locked(ptp_perout_locked[n]),
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.ptp_perout_error(ptp_perout_error[n]),
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.ptp_perout_pulse(ptp_perout_pulse[n])
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);
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end
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end else begin
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assign ptp_perout_locked = 0;
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assign ptp_perout_error = 0;
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assign ptp_perout_pulse = 0;
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end
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endgenerate
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endmodule
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`resetall
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