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320 lines
11 KiB
Verilog
320 lines
11 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Statistics counter
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*/
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module stats_counter #
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(
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// Statistics counter increment width (bits)
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parameter STAT_INC_WIDTH = 16,
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// Statistics counter ID width (bits)
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parameter STAT_ID_WIDTH = 8,
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// Statistics counter (bits)
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parameter STAT_COUNT_WIDTH = 32,
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// Width of AXI lite data bus in bits
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parameter AXIL_DATA_WIDTH = 32,
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// Width of AXI lite address bus in bits
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parameter AXIL_ADDR_WIDTH = STAT_ID_WIDTH+$clog2(((AXIL_DATA_WIDTH > STAT_COUNT_WIDTH ? AXIL_DATA_WIDTH : STAT_COUNT_WIDTH)+7)/8),
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// Width of AXI lite wstrb (width of data bus in words)
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
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// Pipeline length
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parameter PIPELINE = 2
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Statistics increment input
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*/
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input wire [STAT_INC_WIDTH-1:0] s_axis_stat_tdata,
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input wire [STAT_ID_WIDTH-1:0] s_axis_stat_tid,
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input wire s_axis_stat_tvalid,
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output wire s_axis_stat_tready,
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/*
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* AXI Lite register interface
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*/
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
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input wire [2:0] s_axil_awprot,
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input wire s_axil_awvalid,
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output wire s_axil_awready,
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input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
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input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
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input wire s_axil_wvalid,
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output wire s_axil_wready,
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output wire [1:0] s_axil_bresp,
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output wire s_axil_bvalid,
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input wire s_axil_bready,
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
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input wire [2:0] s_axil_arprot,
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input wire s_axil_arvalid,
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output wire s_axil_arready,
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output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
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output wire [1:0] s_axil_rresp,
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output wire s_axil_rvalid,
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input wire s_axil_rready
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);
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parameter ID_SHIFT = $clog2(((AXIL_DATA_WIDTH > STAT_COUNT_WIDTH ? AXIL_DATA_WIDTH : STAT_COUNT_WIDTH)+7)/8);
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parameter WORD_SELECT_SHIFT = $clog2(AXIL_DATA_WIDTH/8);
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parameter WORD_SELECT_WIDTH = STAT_COUNT_WIDTH > AXIL_DATA_WIDTH ? $clog2((STAT_COUNT_WIDTH+7)/8) - $clog2(AXIL_DATA_WIDTH/8) : 0;
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// check configuration
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initial begin
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if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
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$error("Error: AXI lite interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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if (AXIL_ADDR_WIDTH < STAT_ID_WIDTH+ID_SHIFT) begin
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$error("Error: AXI lite address width too narrow (instance %m)");
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$finish;
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end
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if (PIPELINE < 2) begin
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$error("Error: PIPELINE must be at least 2 (instance %m)");
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$finish;
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end
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end
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reg init_reg = 1'b1, init_next;
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reg [STAT_ID_WIDTH-1:0] init_ptr_reg = 0, init_ptr_next;
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reg op_acc_pipe_hazard;
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reg stage_active;
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reg [PIPELINE-1:0] op_axil_read_pipe_reg = 0, op_axil_read_pipe_next;
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reg [PIPELINE-1:0] op_acc_pipe_reg = 0, op_acc_pipe_next;
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reg [STAT_ID_WIDTH-1:0] mem_addr_pipeline_reg[PIPELINE-1:0], mem_addr_pipeline_next[PIPELINE-1:0];
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reg [WORD_SELECT_WIDTH-1:0] axil_shift_pipeline_reg[PIPELINE-1:0], axil_shift_pipeline_next[PIPELINE-1:0];
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reg [STAT_INC_WIDTH-1:0] stat_inc_pipeline_reg[PIPELINE-1:0], stat_inc_pipeline_next[PIPELINE-1:0];
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reg s_axis_stat_tready_reg = 1'b0, s_axis_stat_tready_next;
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reg s_axil_awready_reg = 0, s_axil_awready_next;
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reg s_axil_wready_reg = 0, s_axil_wready_next;
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reg s_axil_bvalid_reg = 0, s_axil_bvalid_next;
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reg s_axil_arready_reg = 0, s_axil_arready_next;
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reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = 0, s_axil_rdata_next;
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reg s_axil_rvalid_reg = 0, s_axil_rvalid_next;
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(* ramstyle = "no_rw_check" *)
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reg [STAT_COUNT_WIDTH-1:0] mem[2**STAT_ID_WIDTH-1:0];
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reg [STAT_ID_WIDTH-1:0] mem_rd_addr;
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reg [STAT_ID_WIDTH-1:0] mem_wr_addr;
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reg [STAT_COUNT_WIDTH-1:0] mem_wr_data;
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reg mem_wr_en;
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reg [STAT_COUNT_WIDTH-1:0] mem_read_data_reg = 0;
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reg [STAT_COUNT_WIDTH-1:0] mem_read_data_pipeline_reg[PIPELINE-1:1];
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assign s_axis_stat_tready = s_axis_stat_tready_reg;
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assign s_axil_awready = s_axil_awready_reg;
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assign s_axil_wready = s_axil_wready_reg;
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assign s_axil_bresp = 2'b00;
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assign s_axil_bvalid = s_axil_bvalid_reg;
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assign s_axil_arready = s_axil_arready_reg;
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assign s_axil_rdata = s_axil_rdata_reg;
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assign s_axil_rresp = 2'b00;
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assign s_axil_rvalid = s_axil_rvalid_reg;
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wire [STAT_ID_WIDTH-1:0] s_axil_araddr_id = s_axil_araddr >> ID_SHIFT;
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wire [WORD_SELECT_WIDTH-1:0] s_axil_araddr_shift = s_axil_araddr >> WORD_SELECT_SHIFT;
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integer i, j;
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initial begin
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// break up loop to work around iteration termination
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for (i = 0; i < 2**STAT_ID_WIDTH; i = i + 2**(STAT_ID_WIDTH/2)) begin
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for (j = i; j < i + 2**(STAT_ID_WIDTH/2); j = j + 1) begin
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mem[j] = 0;
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end
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end
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for (i = 0; i < PIPELINE; i = i + 1) begin
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mem_addr_pipeline_reg[i] = 0;
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axil_shift_pipeline_reg[i] = 0;
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stat_inc_pipeline_reg[i] = 0;
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end
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end
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always @* begin
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init_next = init_reg;
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init_ptr_next = init_ptr_reg;
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op_axil_read_pipe_next = {op_axil_read_pipe_reg, 1'b0};
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op_acc_pipe_next = {op_acc_pipe_reg, 1'b0};
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mem_addr_pipeline_next[0] = 0;
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axil_shift_pipeline_next[0] = 0;
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stat_inc_pipeline_next[0] = 0;
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for (j = 1; j < PIPELINE; j = j + 1) begin
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mem_addr_pipeline_next[j] = mem_addr_pipeline_reg[j-1];
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axil_shift_pipeline_next[j] = axil_shift_pipeline_reg[j-1];
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stat_inc_pipeline_next[j] = stat_inc_pipeline_reg[j-1];
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end
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s_axis_stat_tready_next = 1'b0;
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s_axil_awready_next = 1'b0;
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s_axil_wready_next = 1'b0;
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s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
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s_axil_arready_next = 1'b0;
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s_axil_rdata_next = s_axil_rdata_reg;
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s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready;
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mem_rd_addr = 0;
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mem_wr_addr = mem_addr_pipeline_reg[PIPELINE-1];
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mem_wr_data = mem_read_data_pipeline_reg[PIPELINE-1] + stat_inc_pipeline_reg[PIPELINE-1];
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mem_wr_en = 0;
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op_acc_pipe_hazard = 1'b0;
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stage_active = 1'b0;
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for (j = 0; j < PIPELINE; j = j + 1) begin
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stage_active = op_axil_read_pipe_reg[j] || op_acc_pipe_reg[j];
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op_acc_pipe_hazard = op_acc_pipe_hazard || (stage_active && mem_addr_pipeline_reg[j] == s_axis_stat_tid);
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end
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// discard writes
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if (s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!s_axil_awready && !s_axil_wready)) begin
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s_axil_awready_next = 1'b1;
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s_axil_wready_next = 1'b1;
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s_axil_bvalid_next = 1'b1;
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end
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// pipeline stage 0 - accept request
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if (init_reg) begin
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init_ptr_next = init_ptr_reg + 1;
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mem_wr_addr = init_ptr_reg;
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mem_wr_data = 0;
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mem_wr_en = 1'b1;
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if (&init_ptr_reg) begin
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init_next = 1'b0;
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end
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end else if (s_axil_arvalid && (!s_axil_rvalid || s_axil_rready) && !op_axil_read_pipe_reg) begin
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// AXIL read
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op_axil_read_pipe_next[0] = 1'b1;
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s_axil_arready_next = 1'b1;
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mem_rd_addr = s_axil_araddr_id;
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mem_addr_pipeline_next[0] = s_axil_araddr_id;
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axil_shift_pipeline_next[0] = s_axil_araddr_shift;
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end else if (s_axis_stat_tvalid && !s_axis_stat_tready && !op_acc_pipe_hazard) begin
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// accumulate
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op_acc_pipe_next[0] = 1'b1;
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s_axis_stat_tready_next = 1'b1;
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stat_inc_pipeline_next[0] = s_axis_stat_tdata;
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mem_rd_addr = s_axis_stat_tid;
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mem_addr_pipeline_next[0] = s_axis_stat_tid;
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end
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// read complete, perform operation
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if (op_acc_pipe_reg[PIPELINE-1]) begin
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// accumulate
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mem_wr_addr = mem_addr_pipeline_reg[PIPELINE-1];
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mem_wr_data = mem_read_data_pipeline_reg[PIPELINE-1] + stat_inc_pipeline_reg[PIPELINE-1];
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mem_wr_en = 1'b1;
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end else if (op_axil_read_pipe_reg[PIPELINE-1]) begin
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// AXIL read
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s_axil_rvalid_next = 1'b1;
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s_axil_rdata_next = 0;
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if (STAT_COUNT_WIDTH > AXIL_DATA_WIDTH) begin
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s_axil_rdata_next = mem_read_data_pipeline_reg[PIPELINE-1] >> axil_shift_pipeline_reg[PIPELINE-1]*AXIL_DATA_WIDTH;
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end else begin
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s_axil_rdata_next = mem_read_data_pipeline_reg[PIPELINE-1];
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end
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end
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end
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always @(posedge clk) begin
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init_reg <= init_next;
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init_ptr_reg <= init_ptr_next;
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op_axil_read_pipe_reg <= op_axil_read_pipe_next;
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op_acc_pipe_reg <= op_acc_pipe_next;
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s_axis_stat_tready_reg <= s_axis_stat_tready_next;
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s_axil_awready_reg <= s_axil_awready_next;
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s_axil_wready_reg <= s_axil_wready_next;
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s_axil_bvalid_reg <= s_axil_bvalid_next;
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s_axil_arready_reg <= s_axil_arready_next;
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s_axil_rdata_reg <= s_axil_rdata_next;
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s_axil_rvalid_reg <= s_axil_rvalid_next;
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for (i = 0; i < PIPELINE; i = i + 1) begin
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mem_addr_pipeline_reg[i] <= mem_addr_pipeline_next[i];
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axil_shift_pipeline_reg[i] <= axil_shift_pipeline_next[i];
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stat_inc_pipeline_reg[i] <= stat_inc_pipeline_next[i];
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end
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if (mem_wr_en) begin
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mem[mem_wr_addr] <= mem_wr_data;
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end
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mem_read_data_reg <= mem[mem_rd_addr];
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mem_read_data_pipeline_reg[1] <= mem_read_data_reg;
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for (i = 2; i < PIPELINE; i = i + 1) begin
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mem_read_data_pipeline_reg[i] <= mem_read_data_pipeline_reg[i-1];
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end
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if (rst) begin
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init_reg <= 1'b1;
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init_ptr_reg <= 0;
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op_axil_read_pipe_reg <= 0;
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op_acc_pipe_reg <= 0;
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s_axis_stat_tready_reg <= 1'b0;
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s_axil_awready_reg <= 1'b0;
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s_axil_wready_reg <= 1'b0;
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s_axil_bvalid_reg <= 1'b0;
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s_axil_arready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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