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120 lines
3.5 KiB
Verilog
120 lines
3.5 KiB
Verilog
/*
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Copyright (c) 2013 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream FIFO
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*/
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module axis_fifo #
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(
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parameter ADDR_WIDTH = 12,
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parameter DATA_WIDTH = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser
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);
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reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
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reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {DATA_WIDTH{1'b0}}};
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//(* RAM_STYLE="BLOCK" *)
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reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
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reg output_read = 1'b0;
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reg output_axis_tvalid_reg = 1'b0;
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wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tdata};
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// full when first MSB different but rest same
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wire full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
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(wr_ptr[ADDR_WIDTH-1:0] == rd_ptr[ADDR_WIDTH-1:0]));
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// empty when pointers match exactly
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wire empty = wr_ptr == rd_ptr;
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wire write = input_axis_tvalid & ~full;
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wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
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assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_out_reg;
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assign input_axis_tready = ~full;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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// write
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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wr_ptr <= 0;
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end else if (write) begin
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mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
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wr_ptr <= wr_ptr + 1;
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end
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end
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// read
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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rd_ptr <= 0;
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end else if (read) begin
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data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
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rd_ptr <= rd_ptr + 1;
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end
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end
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// source ready output
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
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output_axis_tvalid_reg <= ~empty;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_reg;
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end
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end
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endmodule
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