mirror of
https://github.com/corundum/corundum.git
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647 lines
18 KiB
Verilog
647 lines
18 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 125MHz LVDS
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* Reset: Push button, active low
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*/
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input wire clk_125mhz_p,
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input wire clk_125mhz_n,
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input wire reset,
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/*
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* GPIO
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*/
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input wire btnu,
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input wire btnl,
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input wire btnd,
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input wire btnr,
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input wire btnc,
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input wire [3:0] sw,
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output wire [7:0] led,
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/*
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* I2C for board management
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*/
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inout wire i2c_scl,
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inout wire i2c_sda,
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/*
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* Ethernet: QSFP28
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*/
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input wire qsfp_rx1_p,
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input wire qsfp_rx1_n,
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// input wire qsfp_rx2_p,
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// input wire qsfp_rx2_n,
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// input wire qsfp_rx3_p,
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// input wire qsfp_rx3_n,
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// input wire qsfp_rx4_p,
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// input wire qsfp_rx4_n,
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output wire qsfp_tx1_p,
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output wire qsfp_tx1_n,
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// output wire qsfp_tx2_p,
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// output wire qsfp_tx2_n,
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// output wire qsfp_tx3_p,
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// output wire qsfp_tx3_n,
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// output wire qsfp_tx4_p,
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// output wire qsfp_tx4_n,
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input wire qsfp_mgt_refclk_0_p,
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input wire qsfp_mgt_refclk_0_n,
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// input wire qsfp_mgt_refclk_1_p,
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// input wire qsfp_mgt_refclk_1_n,
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// output wire qsfp_recclk_p,
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// output wire qsfp_recclk_n,
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output wire qsfp_modsell,
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output wire qsfp_resetl,
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input wire qsfp_modprsl,
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input wire qsfp_intl,
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output wire qsfp_lpmode,
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/*
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* Ethernet: 1000BASE-T SGMII
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*/
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input wire phy_sgmii_rx_p,
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input wire phy_sgmii_rx_n,
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output wire phy_sgmii_tx_p,
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output wire phy_sgmii_tx_n,
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input wire phy_sgmii_clk_p,
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input wire phy_sgmii_clk_n,
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output wire phy_reset_n,
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input wire phy_int_n,
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/*
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* UART: 500000 bps, 8N1
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*/
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input wire uart_rxd,
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output wire uart_txd,
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output wire uart_rts,
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input wire uart_cts
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);
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// Clock and reset
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wire clk_125mhz_ibufg;
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wire clk_125mhz_mmcm_out;
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// Internal 125 MHz clock
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst = reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_125mhz_ibufg_inst (
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.O (clk_125mhz_ibufg),
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.I (clk_125mhz_p),
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.IB (clk_125mhz_n)
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);
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// MMCM instance
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// 125 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 600 MHz to 1440 MHz
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// M = 5, D = 1 sets Fvco = 625 MHz (in range)
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// Divide by 5 to get output frequency of 125 MHz
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MMCME3_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(5),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(5),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(8.0),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_125mhz_ibufg),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.sync_reset_out(rst_125mhz_int)
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);
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// GPIO
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wire btnu_int;
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wire btnl_int;
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wire btnd_int;
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wire btnr_int;
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wire btnc_int;
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wire [3:0] sw_int;
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debounce_switch #(
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.WIDTH(9),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({btnu,
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btnl,
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btnd,
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btnr,
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btnc,
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sw}),
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.out({btnu_int,
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btnl_int,
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btnd_int,
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btnr_int,
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btnc_int,
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sw_int})
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);
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wire uart_rxd_int;
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wire uart_cts_int;
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sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_125mhz_int),
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.in({uart_rxd, uart_cts}),
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.out({uart_rxd_int, uart_cts_int})
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);
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// SI570 I2C
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wire i2c_scl_i;
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wire i2c_scl_o;
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wire i2c_scl_t;
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wire i2c_sda_i;
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wire i2c_sda_o;
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wire i2c_sda_t;
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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wire [6:0] si570_i2c_cmd_address;
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wire si570_i2c_cmd_start;
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wire si570_i2c_cmd_read;
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wire si570_i2c_cmd_write;
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wire si570_i2c_cmd_write_multiple;
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wire si570_i2c_cmd_stop;
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wire si570_i2c_cmd_valid;
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wire si570_i2c_cmd_ready;
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wire [7:0] si570_i2c_data;
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wire si570_i2c_data_valid;
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wire si570_i2c_data_ready;
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wire si570_i2c_data_last;
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wire si570_i2c_init_busy;
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// delay start by ~10 ms
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reg [20:0] si570_i2c_init_start_delay = 21'd0;
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always @(posedge clk_125mhz_int) begin
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if (rst_125mhz_int) begin
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si570_i2c_init_start_delay <= 21'd0;
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end else begin
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if (!si570_i2c_init_start_delay[20]) begin
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si570_i2c_init_start_delay <= si570_i2c_init_start_delay + 21'd1;
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end
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end
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end
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si570_i2c_init
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si570_i2c_init_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.cmd_address(si570_i2c_cmd_address),
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.cmd_start(si570_i2c_cmd_start),
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.cmd_read(si570_i2c_cmd_read),
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.cmd_write(si570_i2c_cmd_write),
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.cmd_write_multiple(si570_i2c_cmd_write_multiple),
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.cmd_stop(si570_i2c_cmd_stop),
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.cmd_valid(si570_i2c_cmd_valid),
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.cmd_ready(si570_i2c_cmd_ready),
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.data_out(si570_i2c_data),
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.data_out_valid(si570_i2c_data_valid),
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.data_out_ready(si570_i2c_data_ready),
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.data_out_last(si570_i2c_data_last),
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.busy(si570_i2c_init_busy),
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.start(si570_i2c_init_start_delay[20])
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);
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i2c_master
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si570_i2c_master (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.cmd_address(si570_i2c_cmd_address),
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.cmd_start(si570_i2c_cmd_start),
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.cmd_read(si570_i2c_cmd_read),
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.cmd_write(si570_i2c_cmd_write),
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.cmd_write_multiple(si570_i2c_cmd_write_multiple),
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.cmd_stop(si570_i2c_cmd_stop),
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.cmd_valid(si570_i2c_cmd_valid),
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.cmd_ready(si570_i2c_cmd_ready),
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.data_in(si570_i2c_data),
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.data_in_valid(si570_i2c_data_valid),
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.data_in_ready(si570_i2c_data_ready),
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.data_in_last(si570_i2c_data_last),
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.data_out(),
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.data_out_valid(),
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.data_out_ready(1),
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.data_out_last(),
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.scl_i(i2c_scl_i),
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.scl_o(i2c_scl_o),
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.scl_t(i2c_scl_t),
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.sda_i(i2c_sda_i),
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.sda_o(i2c_sda_o),
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.sda_t(i2c_sda_t),
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.busy(),
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.bus_control(),
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.bus_active(),
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.missed_ack(),
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.prescale(800),
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.stop_on_idle(1)
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);
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// XGMII 10G PHY
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assign qsfp_modsell = 1'b0;
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assign qsfp_resetl = 1'b1;
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assign qsfp_lpmode = 1'b0;
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wire [63:0] qsfp_txd_1_int;
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wire [7:0] qsfp_txc_1_int;
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wire [63:0] qsfp_rxd_1_int;
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wire [7:0] qsfp_rxc_1_int;
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wire [63:0] qsfp_txd_2_int;
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wire [7:0] qsfp_txc_2_int;
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wire [63:0] qsfp_rxd_2_int = 64'h0707070707070707;
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wire [7:0] qsfp_rxc_2_int = 8'hff;
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wire [63:0] qsfp_txd_3_int;
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wire [7:0] qsfp_txc_3_int;
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wire [63:0] qsfp_rxd_3_int = 64'h0707070707070707;
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wire [7:0] qsfp_rxc_3_int = 8'hff;
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wire [63:0] qsfp_txd_4_int;
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wire [7:0] qsfp_txc_4_int;
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wire [63:0] qsfp_rxd_4_int = 64'h0707070707070707;
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wire [7:0] qsfp_rxc_4_int = 8'hff;
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wire [535:0] configuration_vector;
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wire [447:0] status_vector;
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wire [7:0] core_status;
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assign configuration_vector[0] = 1'b0; // PMA Loopback Enable
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assign configuration_vector[14:1] = 0;
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assign configuration_vector[15] = 1'b0; // PMA Reset
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assign configuration_vector[16] = 1'b0; // Global PMD TX Disable
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assign configuration_vector[109:17] = 0;
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assign configuration_vector[110] = 1'b0; // PCS Loopback Enable
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assign configuration_vector[111] = 1'b0; // PCS Reset
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assign configuration_vector[169:112] = 58'd0; // 10GBASE-R Test Pattern Seed A0-3
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assign configuration_vector[175:170] = 0;
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assign configuration_vector[233:176] = 58'd0; // 10GBASE-R Test Pattern Seed B0-3
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assign configuration_vector[239:234] = 0;
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assign configuration_vector[240] = 1'b0; // Data Pattern Select
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assign configuration_vector[241] = 1'b0; // Test Pattern Select
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assign configuration_vector[242] = 1'b0; // RX Test Pattern Checking Enable
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assign configuration_vector[243] = 1'b0; // TX Test Pattern Enable
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assign configuration_vector[244] = 1'b0; // PRBS31 TX Test Pattern Enable
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assign configuration_vector[245] = 1'b0; // PRBS31 RX Test Pattern Checking Enable
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assign configuration_vector[383:246] = 0;
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assign configuration_vector[399:384] = 16'h4C4B; // 125 us timer control
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assign configuration_vector[511:400] = 0;
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assign configuration_vector[512] = 1'b0; // Set PMA Link Status
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assign configuration_vector[513] = 1'b0; // Clear PMA/PMD Link Faults
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assign configuration_vector[515:514] = 0;
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assign configuration_vector[516] = 1'b0; // Set PCS Link Status
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assign configuration_vector[517] = 1'b0; // Clear PCS Link Faults
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assign configuration_vector[518] = 1'b0; // Clear 10GBASE-R Status 2
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assign configuration_vector[519] = 1'b0; // Clear 10GBASE-R Test Pattern Error Counter
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assign configuration_vector[535:520] = 0;
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wire drp_gnt;
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wire gt_drprdy;
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wire [15:0] gt_drpdo;
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wire gt_drpen;
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wire gt_drpwe;
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wire [15:0] gt_drpaddr;
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wire [15:0] gt_drpdi;
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ten_gig_eth_pcs_pma_0
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ten_gig_eth_pcs_pma_inst (
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.refclk_p(qsfp_mgt_refclk_0_p),
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.refclk_n(qsfp_mgt_refclk_0_n),
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.dclk(clk_125mhz_int),
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.coreclk_out(),
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.reset(rst_125mhz_int | si570_i2c_init_busy),
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.sim_speedup_control(1'b0),
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.qpll0outclk_out(),
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.qpll0outrefclk_out(),
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.qpll0lock_out(),
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.rxrecclk_out(),
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.txusrclk_out(),
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.txusrclk2_out(clk_156mhz_int),
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.gttxreset_out(),
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.gtrxreset_out(),
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.txuserrdy_out(),
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.areset_datapathclk_out(rst_156mhz_int),
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.areset_coreclk_out(),
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.reset_counter_done_out(),
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.xgmii_txd(qsfp_txd_1_int),
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.xgmii_txc(qsfp_txc_1_int),
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.xgmii_rxd(qsfp_rxd_1_int),
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.xgmii_rxc(qsfp_rxc_1_int),
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.txp(qsfp_tx1_p),
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.txn(qsfp_tx1_n),
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.rxp(qsfp_rx1_p),
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.rxn(qsfp_rx1_n),
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.resetdone_out(),
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.signal_detect(1'b1),
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.tx_fault(1'b0),
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.drp_req(drp_gnt),
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.drp_gnt(drp_gnt),
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.core_to_gt_drprdy(gt_drprdy),
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.core_to_gt_drpdo(gt_drpdo),
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.core_to_gt_drpen(gt_drpen),
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.core_to_gt_drpwe(gt_drpwe),
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.core_to_gt_drpaddr(gt_drpaddr),
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.core_to_gt_drpdi(gt_drpdi),
|
|
|
|
.gt_drprdy(gt_drprdy),
|
|
.gt_drpdo(gt_drpdo),
|
|
.gt_drpen(gt_drpen),
|
|
.gt_drpwe(gt_drpwe),
|
|
.gt_drpaddr(gt_drpaddr),
|
|
.gt_drpdi(gt_drpdi),
|
|
|
|
.tx_disable(),
|
|
.configuration_vector(configuration_vector),
|
|
.status_vector(status_vector),
|
|
.pma_pmd_type(3'b101),
|
|
.core_status(core_status)
|
|
);
|
|
|
|
// SGMII interface to PHY
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wire phy_gmii_clk_int;
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wire phy_gmii_rst_int;
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wire phy_gmii_clk_en_int;
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wire [7:0] phy_gmii_txd_int;
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wire phy_gmii_tx_en_int;
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wire phy_gmii_tx_er_int;
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wire [7:0] phy_gmii_rxd_int;
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wire phy_gmii_rx_dv_int;
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wire phy_gmii_rx_er_int;
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|
|
|
wire [15:0] gig_eth_pcspma_status_vector;
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|
|
|
wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0];
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wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1];
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wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2];
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wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3];
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wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4];
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wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5];
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|
wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6];
|
|
wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7];
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|
wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8];
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|
wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10];
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|
wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12];
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|
wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13];
|
|
wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14];
|
|
|
|
wire [4:0] gig_eth_pcspma_config_vector;
|
|
|
|
assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable
|
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assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate
|
|
assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down
|
|
assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable
|
|
assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable
|
|
|
|
wire [15:0] gig_eth_pcspma_an_config_vector;
|
|
|
|
assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status
|
|
assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
|
|
assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex
|
|
assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
|
|
assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved
|
|
assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
|
|
assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved
|
|
assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
|
|
assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved
|
|
assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII
|
|
|
|
gig_ethernet_pcs_pma_0
|
|
gig_eth_pcspma (
|
|
// SGMII
|
|
.txp (phy_sgmii_tx_p),
|
|
.txn (phy_sgmii_tx_n),
|
|
.rxp (phy_sgmii_rx_p),
|
|
.rxn (phy_sgmii_rx_n),
|
|
|
|
// Ref clock from PHY
|
|
.refclk625_p (phy_sgmii_clk_p),
|
|
.refclk625_n (phy_sgmii_clk_n),
|
|
|
|
// async reset
|
|
.reset (rst_125mhz_int),
|
|
|
|
// clock and reset outputs
|
|
.clk125_out (phy_gmii_clk_int),
|
|
.clk625_out (),
|
|
.clk312_out (),
|
|
.rst_125_out (phy_gmii_rst_int),
|
|
.idelay_rdy_out (),
|
|
.mmcm_locked_out (),
|
|
|
|
// MAC clocking
|
|
.sgmii_clk_r (),
|
|
.sgmii_clk_f (),
|
|
.sgmii_clk_en (phy_gmii_clk_en_int),
|
|
|
|
// Speed control
|
|
.speed_is_10_100 (gig_eth_pcspma_status_speed != 2'b10),
|
|
.speed_is_100 (gig_eth_pcspma_status_speed == 2'b01),
|
|
|
|
// Internal GMII
|
|
.gmii_txd (phy_gmii_txd_int),
|
|
.gmii_tx_en (phy_gmii_tx_en_int),
|
|
.gmii_tx_er (phy_gmii_tx_er_int),
|
|
.gmii_rxd (phy_gmii_rxd_int),
|
|
.gmii_rx_dv (phy_gmii_rx_dv_int),
|
|
.gmii_rx_er (phy_gmii_rx_er_int),
|
|
.gmii_isolate (),
|
|
|
|
// Configuration
|
|
.configuration_vector (gig_eth_pcspma_config_vector),
|
|
|
|
.an_interrupt (),
|
|
.an_adv_config_vector (gig_eth_pcspma_an_config_vector),
|
|
.an_restart_config (1'b0),
|
|
|
|
// Status
|
|
.status_vector (gig_eth_pcspma_status_vector),
|
|
.signal_detect (1'b1)
|
|
);
|
|
|
|
wire [7:0] led_int;
|
|
|
|
assign led = sw[0] ? {7'd0, core_status[0]} : led_int;
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz_int),
|
|
.rst(rst_156mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.btnu(btnu_int),
|
|
.btnl(btnl_int),
|
|
.btnd(btnd_int),
|
|
.btnr(btnr_int),
|
|
.btnc(btnc_int),
|
|
.sw(sw_int),
|
|
.led(led_int),
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.qsfp_txd_1(qsfp_txd_1_int),
|
|
.qsfp_txc_1(qsfp_txc_1_int),
|
|
.qsfp_rxd_1(qsfp_rxd_1_int),
|
|
.qsfp_rxc_1(qsfp_rxc_1_int),
|
|
.qsfp_txd_2(qsfp_txd_2_int),
|
|
.qsfp_txc_2(qsfp_txc_2_int),
|
|
.qsfp_rxd_2(qsfp_rxd_2_int),
|
|
.qsfp_rxc_2(qsfp_rxc_2_int),
|
|
.qsfp_txd_3(qsfp_txd_3_int),
|
|
.qsfp_txc_3(qsfp_txc_3_int),
|
|
.qsfp_rxd_3(qsfp_rxd_3_int),
|
|
.qsfp_rxc_3(qsfp_rxc_3_int),
|
|
.qsfp_txd_4(qsfp_txd_4_int),
|
|
.qsfp_txc_4(qsfp_txc_4_int),
|
|
.qsfp_rxd_4(qsfp_rxd_4_int),
|
|
.qsfp_rxc_4(qsfp_rxc_4_int),
|
|
/*
|
|
* Ethernet: 1000BASE-T SGMII
|
|
*/
|
|
.phy_gmii_clk(phy_gmii_clk_int),
|
|
.phy_gmii_rst(phy_gmii_rst_int),
|
|
.phy_gmii_clk_en(phy_gmii_clk_en_int),
|
|
.phy_gmii_rxd(phy_gmii_rxd_int),
|
|
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
|
|
.phy_gmii_rx_er(phy_gmii_rx_er_int),
|
|
.phy_gmii_txd(phy_gmii_txd_int),
|
|
.phy_gmii_tx_en(phy_gmii_tx_en_int),
|
|
.phy_gmii_tx_er(phy_gmii_tx_er_int),
|
|
.phy_reset_n(phy_reset_n),
|
|
.phy_int_n(phy_int_n),
|
|
/*
|
|
* UART: 115200 bps, 8N1
|
|
*/
|
|
.uart_rxd(uart_rxd_int),
|
|
.uart_txd(uart_txd),
|
|
.uart_rts(uart_rts),
|
|
.uart_cts(uart_cts_int)
|
|
);
|
|
|
|
endmodule
|