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346 lines
11 KiB
Verilog
346 lines
11 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* IPv4 block, ethernet frame interface
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*/
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module ip
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame input
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*/
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input wire s_eth_hdr_valid,
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output wire s_eth_hdr_ready,
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input wire [47:0] s_eth_dest_mac,
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input wire [47:0] s_eth_src_mac,
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input wire [15:0] s_eth_type,
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input wire [7:0] s_eth_payload_axis_tdata,
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input wire s_eth_payload_axis_tvalid,
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output wire s_eth_payload_axis_tready,
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input wire s_eth_payload_axis_tlast,
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input wire s_eth_payload_axis_tuser,
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/*
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* Ethernet frame output
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*/
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output wire m_eth_hdr_valid,
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input wire m_eth_hdr_ready,
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output wire [47:0] m_eth_dest_mac,
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output wire [47:0] m_eth_src_mac,
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output wire [15:0] m_eth_type,
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output wire [7:0] m_eth_payload_axis_tdata,
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output wire m_eth_payload_axis_tvalid,
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input wire m_eth_payload_axis_tready,
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output wire m_eth_payload_axis_tlast,
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output wire m_eth_payload_axis_tuser,
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/*
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* ARP requests
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*/
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output wire arp_request_valid,
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input wire arp_request_ready,
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output wire [31:0] arp_request_ip,
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input wire arp_response_valid,
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output wire arp_response_ready,
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input wire arp_response_error,
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input wire [47:0] arp_response_mac,
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/*
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* IP input
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*/
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input wire s_ip_hdr_valid,
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output wire s_ip_hdr_ready,
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input wire [5:0] s_ip_dscp,
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input wire [1:0] s_ip_ecn,
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input wire [15:0] s_ip_length,
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input wire [7:0] s_ip_ttl,
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input wire [7:0] s_ip_protocol,
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input wire [31:0] s_ip_source_ip,
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input wire [31:0] s_ip_dest_ip,
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input wire [7:0] s_ip_payload_axis_tdata,
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input wire s_ip_payload_axis_tvalid,
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output wire s_ip_payload_axis_tready,
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input wire s_ip_payload_axis_tlast,
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input wire s_ip_payload_axis_tuser,
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/*
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* IP output
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*/
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output wire m_ip_hdr_valid,
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input wire m_ip_hdr_ready,
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output wire [47:0] m_ip_eth_dest_mac,
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output wire [47:0] m_ip_eth_src_mac,
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output wire [15:0] m_ip_eth_type,
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output wire [3:0] m_ip_version,
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output wire [3:0] m_ip_ihl,
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output wire [5:0] m_ip_dscp,
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output wire [1:0] m_ip_ecn,
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output wire [15:0] m_ip_length,
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output wire [15:0] m_ip_identification,
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output wire [2:0] m_ip_flags,
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output wire [12:0] m_ip_fragment_offset,
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output wire [7:0] m_ip_ttl,
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output wire [7:0] m_ip_protocol,
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output wire [15:0] m_ip_header_checksum,
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output wire [31:0] m_ip_source_ip,
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output wire [31:0] m_ip_dest_ip,
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output wire [7:0] m_ip_payload_axis_tdata,
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output wire m_ip_payload_axis_tvalid,
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input wire m_ip_payload_axis_tready,
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output wire m_ip_payload_axis_tlast,
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output wire m_ip_payload_axis_tuser,
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/*
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* Status
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*/
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output wire rx_busy,
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output wire tx_busy,
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output wire rx_error_header_early_termination,
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output wire rx_error_payload_early_termination,
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output wire rx_error_invalid_header,
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output wire rx_error_invalid_checksum,
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output wire tx_error_payload_early_termination,
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output wire tx_error_arp_failed,
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/*
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* Configuration
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*/
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input wire [47:0] local_mac,
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input wire [31:0] local_ip
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);
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_ARP_QUERY = 2'd1,
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STATE_WAIT_PACKET = 2'd2;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg outgoing_ip_hdr_valid_reg = 1'b0, outgoing_ip_hdr_valid_next;
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wire outgoing_ip_hdr_ready;
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reg [47:0] outgoing_eth_dest_mac_reg = 48'h000000000000, outgoing_eth_dest_mac_next;
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wire outgoing_ip_payload_axis_tready;
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/*
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* IP frame processing
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*/
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ip_eth_rx
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ip_eth_rx_inst (
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.clk(clk),
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.rst(rst),
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// Ethernet frame input
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.s_eth_hdr_valid(s_eth_hdr_valid),
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.s_eth_hdr_ready(s_eth_hdr_ready),
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.s_eth_dest_mac(s_eth_dest_mac),
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.s_eth_src_mac(s_eth_src_mac),
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.s_eth_type(s_eth_type),
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.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
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.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
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.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
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.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
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.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
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// IP frame output
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.m_ip_hdr_valid(m_ip_hdr_valid),
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.m_ip_hdr_ready(m_ip_hdr_ready),
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.m_eth_dest_mac(m_ip_eth_dest_mac),
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.m_eth_src_mac(m_ip_eth_src_mac),
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.m_eth_type(m_ip_eth_type),
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.m_ip_version(m_ip_version),
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.m_ip_ihl(m_ip_ihl),
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.m_ip_dscp(m_ip_dscp),
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.m_ip_ecn(m_ip_ecn),
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.m_ip_length(m_ip_length),
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.m_ip_identification(m_ip_identification),
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.m_ip_flags(m_ip_flags),
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.m_ip_fragment_offset(m_ip_fragment_offset),
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.m_ip_ttl(m_ip_ttl),
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.m_ip_protocol(m_ip_protocol),
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.m_ip_header_checksum(m_ip_header_checksum),
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.m_ip_source_ip(m_ip_source_ip),
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.m_ip_dest_ip(m_ip_dest_ip),
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.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
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.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
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.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
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.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
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.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
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// Status signals
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.busy(rx_busy),
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.error_header_early_termination(rx_error_header_early_termination),
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.error_payload_early_termination(rx_error_payload_early_termination),
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.error_invalid_header(rx_error_invalid_header),
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.error_invalid_checksum(rx_error_invalid_checksum)
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);
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ip_eth_tx
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ip_eth_tx_inst (
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.clk(clk),
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.rst(rst),
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// IP frame input
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.s_ip_hdr_valid(outgoing_ip_hdr_valid_reg),
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.s_ip_hdr_ready(outgoing_ip_hdr_ready),
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.s_eth_dest_mac(outgoing_eth_dest_mac_reg),
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.s_eth_src_mac(local_mac),
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.s_eth_type(16'h0800),
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.s_ip_dscp(s_ip_dscp),
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.s_ip_ecn(s_ip_ecn),
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.s_ip_length(s_ip_length),
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.s_ip_identification(16'd0),
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.s_ip_flags(3'b010),
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.s_ip_fragment_offset(13'd0),
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.s_ip_ttl(s_ip_ttl),
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.s_ip_protocol(s_ip_protocol),
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.s_ip_source_ip(s_ip_source_ip),
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.s_ip_dest_ip(s_ip_dest_ip),
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.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
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.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
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.s_ip_payload_axis_tready(outgoing_ip_payload_axis_tready),
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.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
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.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
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// Ethernet frame output
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.m_eth_hdr_valid(m_eth_hdr_valid),
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.m_eth_hdr_ready(m_eth_hdr_ready),
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.m_eth_dest_mac(m_eth_dest_mac),
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.m_eth_src_mac(m_eth_src_mac),
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.m_eth_type(m_eth_type),
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.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
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.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
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.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
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.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
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.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
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// Status signals
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.busy(tx_busy),
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.error_payload_early_termination(tx_error_payload_early_termination)
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);
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reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
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reg arp_request_valid_reg = 1'b0, arp_request_valid_next;
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reg arp_response_ready_reg = 1'b0, arp_response_ready_next;
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reg drop_packet_reg = 1'b0, drop_packet_next;
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assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
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assign s_ip_payload_axis_tready = outgoing_ip_payload_axis_tready || drop_packet_reg;
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assign arp_request_valid = arp_request_valid_reg;
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assign arp_request_ip = s_ip_dest_ip;
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assign arp_response_ready = arp_response_ready_reg;
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assign tx_error_arp_failed = arp_response_error;
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always @* begin
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state_next = STATE_IDLE;
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arp_request_valid_next = arp_request_valid_reg && !arp_request_ready;
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arp_response_ready_next = 1'b0;
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drop_packet_next = 1'b0;
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s_ip_hdr_ready_next = 1'b0;
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outgoing_ip_hdr_valid_next = outgoing_ip_hdr_valid_reg && !outgoing_ip_hdr_ready;
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outgoing_eth_dest_mac_next = outgoing_eth_dest_mac_reg;
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case (state_reg)
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STATE_IDLE: begin
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// wait for outgoing packet
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if (s_ip_hdr_valid) begin
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// initiate ARP request
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arp_request_valid_next = 1'b1;
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arp_response_ready_next = 1'b1;
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state_next = STATE_ARP_QUERY;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_ARP_QUERY: begin
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arp_response_ready_next = 1'b1;
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if (arp_response_valid) begin
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// wait for ARP reponse
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if (arp_response_error) begin
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// did not get MAC address; drop packet
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s_ip_hdr_ready_next = 1'b1;
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drop_packet_next = 1'b1;
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state_next = STATE_WAIT_PACKET;
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end else begin
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// got MAC address; send packet
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s_ip_hdr_ready_next = 1'b1;
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outgoing_ip_hdr_valid_next = 1'b1;
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outgoing_eth_dest_mac_next = arp_response_mac;
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state_next = STATE_WAIT_PACKET;
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end
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end else begin
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state_next = STATE_ARP_QUERY;
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end
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end
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STATE_WAIT_PACKET: begin
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drop_packet_next = drop_packet_reg;
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// wait for packet transfer to complete
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if (s_ip_payload_axis_tlast && s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WAIT_PACKET;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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arp_request_valid_reg <= 1'b0;
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arp_response_ready_reg <= 1'b0;
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drop_packet_reg <= 1'b0;
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s_ip_hdr_ready_reg <= 1'b0;
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outgoing_ip_hdr_valid_reg <= 1'b0;
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end else begin
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state_reg <= state_next;
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arp_request_valid_reg <= arp_request_valid_next;
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arp_response_ready_reg <= arp_response_ready_next;
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drop_packet_reg <= drop_packet_next;
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s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
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outgoing_ip_hdr_valid_reg <= outgoing_ip_hdr_valid_next;
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end
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outgoing_eth_dest_mac_reg <= outgoing_eth_dest_mac_next;
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end
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endmodule
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`resetall
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