mirror of
https://github.com/corundum/corundum.git
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364 lines
11 KiB
Python
Executable File
364 lines
11 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2015-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import axis_ep
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import eth_ep
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import xgmii_ep
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module = 'axis_xgmii_tx_32'
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testbench = 'test_%s' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("../rtl/lfsr.v")
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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DATA_WIDTH = 32
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KEEP_WIDTH = (DATA_WIDTH/8)
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CTRL_WIDTH = (DATA_WIDTH/8)
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ENABLE_PADDING = 1
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ENABLE_DIC = 1
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MIN_FRAME_LENGTH = 64
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PTP_TS_ENABLE = 0
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PTP_TS_WIDTH = 96
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PTP_TAG_ENABLE = PTP_TS_ENABLE
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PTP_TAG_WIDTH = 16
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USER_WIDTH = (PTP_TAG_WIDTH if PTP_TAG_ENABLE else 0) + 1
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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s_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
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s_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
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s_axis_tvalid = Signal(bool(0))
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s_axis_tlast = Signal(bool(0))
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s_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
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ptp_ts = Signal(intbv(0)[PTP_TS_WIDTH:])
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ifg_delay = Signal(intbv(0)[8:])
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# Outputs
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s_axis_tready = Signal(bool(0))
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xgmii_txd = Signal(intbv(0x07070707)[DATA_WIDTH:])
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xgmii_txc = Signal(intbv(0xf)[CTRL_WIDTH:])
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m_axis_ptp_ts = Signal(intbv(0)[PTP_TS_WIDTH:])
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m_axis_ptp_ts_tag = Signal(intbv(0)[PTP_TAG_WIDTH:])
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m_axis_ptp_ts_valid = Signal(bool(0))
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start_packet = Signal(bool(0))
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error_underflow = Signal(bool(0))
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# sources and sinks
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source_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource()
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source_logic = source.create_logic(
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clk,
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rst,
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tdata=s_axis_tdata,
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tkeep=s_axis_tkeep,
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tvalid=s_axis_tvalid,
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tready=s_axis_tready,
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tlast=s_axis_tlast,
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tuser=s_axis_tuser,
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pause=source_pause,
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name='source'
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)
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sink = xgmii_ep.XGMIISink()
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sink_logic = sink.create_logic(
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clk,
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rst,
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rxd=xgmii_txd,
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rxc=xgmii_txc,
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name='sink'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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s_axis_tdata=s_axis_tdata,
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s_axis_tkeep=s_axis_tkeep,
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s_axis_tvalid=s_axis_tvalid,
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s_axis_tready=s_axis_tready,
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s_axis_tlast=s_axis_tlast,
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s_axis_tuser=s_axis_tuser,
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xgmii_txd=xgmii_txd,
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xgmii_txc=xgmii_txc,
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ptp_ts=ptp_ts,
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m_axis_ptp_ts=m_axis_ptp_ts,
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m_axis_ptp_ts_tag=m_axis_ptp_ts_tag,
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m_axis_ptp_ts_valid=m_axis_ptp_ts_valid,
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ifg_delay=ifg_delay,
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start_packet=start_packet,
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error_underflow=error_underflow
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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ifg_delay.next = 12
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# testbench stimulus
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for payload_len in list(range(1,18))+list(range(40,58)):
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yield clk.posedge
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print("test 1: test packet, length %d" % payload_len)
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current_test.next = 1
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test_frame = eth_ep.EthFrame()
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test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
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test_frame.eth_src_mac = 0x5A5152535455
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test_frame.eth_type = 0x8000
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test_frame.payload = bytearray(range(payload_len))
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test_frame.update_fcs()
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axis_frame = test_frame.build_axis()
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source.send(axis_frame)
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
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eth_frame = eth_ep.EthFrame()
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eth_frame.parse_axis_fcs(rx_frame.data[8:])
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print(hex(eth_frame.eth_fcs))
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print(hex(eth_frame.calc_fcs()))
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assert len(eth_frame.payload.data) == max(payload_len, 46)
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assert eth_frame.eth_fcs == eth_frame.calc_fcs()
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assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
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assert eth_frame.eth_src_mac == test_frame.eth_src_mac
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assert eth_frame.eth_type == test_frame.eth_type
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assert eth_frame.payload.data.index(test_frame.payload.data) == 0
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assert sink.empty()
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yield delay(100)
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yield clk.posedge
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print("test 2: back-to-back packets, length %d" % payload_len)
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current_test.next = 2
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test_frame1 = eth_ep.EthFrame()
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test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
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test_frame1.eth_src_mac = 0x5A5152535455
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test_frame1.eth_type = 0x8000
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test_frame1.payload = bytearray(range(payload_len))
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test_frame1.update_fcs()
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test_frame2 = eth_ep.EthFrame()
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test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
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test_frame2.eth_src_mac = 0x5A5152535455
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test_frame2.eth_type = 0x8000
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test_frame2.payload = bytearray(range(payload_len))
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test_frame2.update_fcs()
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axis_frame1 = test_frame1.build_axis()
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axis_frame2 = test_frame2.build_axis()
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source.send(axis_frame1)
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source.send(axis_frame2)
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
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eth_frame = eth_ep.EthFrame()
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eth_frame.parse_axis_fcs(rx_frame.data[8:])
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print(hex(eth_frame.eth_fcs))
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print(hex(eth_frame.calc_fcs()))
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assert len(eth_frame.payload.data) == max(payload_len, 46)
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assert eth_frame.eth_fcs == eth_frame.calc_fcs()
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assert eth_frame.eth_dest_mac == test_frame1.eth_dest_mac
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assert eth_frame.eth_src_mac == test_frame1.eth_src_mac
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assert eth_frame.eth_type == test_frame1.eth_type
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assert eth_frame.payload.data.index(test_frame1.payload.data) == 0
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
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eth_frame = eth_ep.EthFrame()
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eth_frame.parse_axis_fcs(rx_frame.data[8:])
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print(hex(eth_frame.eth_fcs))
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print(hex(eth_frame.calc_fcs()))
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assert len(eth_frame.payload.data) == max(payload_len, 46)
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assert eth_frame.eth_fcs == eth_frame.calc_fcs()
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assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
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assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
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assert eth_frame.eth_type == test_frame2.eth_type
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assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
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assert sink.empty()
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yield delay(100)
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yield clk.posedge
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print("test 3: tuser assert, length %d" % payload_len)
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current_test.next = 3
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test_frame1 = eth_ep.EthFrame()
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test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
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test_frame1.eth_src_mac = 0x5A5152535455
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test_frame1.eth_type = 0x8000
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test_frame1.payload = bytearray(range(payload_len))
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test_frame1.update_fcs()
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test_frame2 = eth_ep.EthFrame()
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test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
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test_frame2.eth_src_mac = 0x5A5152535455
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test_frame2.eth_type = 0x8000
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test_frame2.payload = bytearray(range(payload_len))
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test_frame2.update_fcs()
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axis_frame1 = test_frame1.build_axis()
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axis_frame2 = test_frame2.build_axis()
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axis_frame1.last_cycle_user = 1
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source.send(axis_frame1)
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source.send(axis_frame2)
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
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assert rx_frame.error[-1]
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# bad packet
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
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eth_frame = eth_ep.EthFrame()
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eth_frame.parse_axis_fcs(rx_frame.data[8:])
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print(hex(eth_frame.eth_fcs))
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print(hex(eth_frame.calc_fcs()))
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assert len(eth_frame.payload.data) == max(payload_len, 46)
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assert eth_frame.eth_fcs == eth_frame.calc_fcs()
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assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
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assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
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assert eth_frame.eth_type == test_frame2.eth_type
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assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
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assert sink.empty()
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yield delay(100)
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for payload_len in list(range(46,54)):
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yield clk.posedge
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print("test 4: test stream, length %d" % payload_len)
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current_test.next = 4
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for i in range(10):
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test_frame = eth_ep.EthFrame()
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test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
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test_frame.eth_src_mac = 0x5A5152535455
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test_frame.eth_type = 0x8000
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test_frame.payload = bytearray(range(payload_len))
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test_frame.update_fcs()
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axis_frame = test_frame.build_axis()
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source.send(axis_frame)
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for i in range(10):
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
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eth_frame = eth_ep.EthFrame()
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eth_frame.parse_axis_fcs(rx_frame.data[8:])
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assert len(eth_frame.payload.data) == max(payload_len, 46)
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assert eth_frame.eth_fcs == eth_frame.calc_fcs()
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assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
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assert eth_frame.eth_src_mac == test_frame.eth_src_mac
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assert eth_frame.eth_type == test_frame.eth_type
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assert eth_frame.payload.data.index(test_frame.payload.data) == 0
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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