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332 lines
9.8 KiB
Verilog
332 lines
9.8 KiB
Verilog
/*
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Copyright (c) 2022 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 50 MHz, 100 MHz
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* Reset: Push button, active low
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*/
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// input wire clk_100_b2a,
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// input wire clk_50_b3a,
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// input wire clk_50_b3c,
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// input wire cpu_reset_n,
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/*
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* GPIO
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*/
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input wire [1:0] button,
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input wire [1:0] sw,
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output wire [3:0] led,
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output wire [3:0] led_bracket,
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/*
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* PCIe: gen 4 x16
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*/
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output wire [15:0] pcie_tx_p,
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output wire [15:0] pcie_tx_n,
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input wire [15:0] pcie_rx_p,
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input wire [15:0] pcie_rx_n,
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input wire [1:0] pcie_refclk_p,
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input wire pcie_perst_n,
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/*
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* Ethernet: QSFP-DD
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*/
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// output wire [7:0] qsfpdda_tx_p,
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// output wire [7:0] qsfpdda_tx_n,
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// input wire [7:0] qsfpdda_rx_p,
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// input wire [7:0] qsfpdda_rx_n,
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// output wire [7:0] qsfpddb_tx_p,
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// output wire [7:0] qsfpddb_tx_n,
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// input wire [7:0] qsfpddb_rx_p,
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// input wire [7:0] qsfpddb_rx_n,
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input wire qsfpdda_refclk_p
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// input wire qsfpddb_refclk_p,
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// input wire qsfpddrsv_refclk_p,
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// output wire qsfpdda_initmode,
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// input wire qsfpdda_interrupt_n,
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// input wire qsfpdda_mod_prs_n,
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// output wire qsfpdda_mod_sel_n,
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// output wire qsfpdda_rst_n,
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// inout wire qsfpdda_scl,
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// inout wire qsfpdda_sda,
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// output wire qsfpddb_initmode,
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// input wire qsfpddb_interrupt_n,
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// input wire qsfpddb_mod_prs_n,
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// output wire qsfpddb_mod_sel_n,
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// output wire qsfpddb_rst_n,
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// inout wire qsfpddb_scl,
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// inout wire qsfpddb_sda
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);
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parameter SEG_COUNT = 2;
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parameter SEG_DATA_WIDTH = 256;
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parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32);
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parameter SEG_HDR_WIDTH = 128;
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parameter SEG_PRFX_WIDTH = 32;
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parameter TX_SEQ_NUM_WIDTH = 6;
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parameter PCIE_TAG_COUNT = 256;
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parameter BAR0_APERTURE = 24;
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parameter BAR2_APERTURE = 24;
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parameter BAR4_APERTURE = 16;
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// Clock and reset
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wire ninit_done;
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reset_release reset_release_inst (
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.ninit_done (ninit_done)
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);
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// wire clk_100mhz = clk_sys_100m_p;
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// wire rst_100mhz;
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// sync_reset #(
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// .N(20)
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// )
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// sync_reset_100mhz_inst (
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// .clk(clk_100mhz),
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// .rst(!cpu_resetn || ninit_done),
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// .out(rst_100mhz)
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// );
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wire coreclkout_hip;
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wire reset_status_n;
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wire clk = coreclkout_hip;
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wire rst = !reset_status_n;
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wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data;
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wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty;
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wire [SEG_COUNT-1:0] rx_st_sop;
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wire [SEG_COUNT-1:0] rx_st_eop;
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wire [SEG_COUNT-1:0] rx_st_valid;
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wire rx_st_ready;
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wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr;
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wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx;
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wire [SEG_COUNT-1:0] rx_st_vf_active = 0;
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wire [SEG_COUNT*3-1:0] rx_st_func_num = 0;
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wire [SEG_COUNT*11-1:0] rx_st_vf_num = 0;
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wire [SEG_COUNT*3-1:0] rx_st_bar_range;
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wire [SEG_COUNT-1:0] rx_st_tlp_abort;
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wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data;
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wire [SEG_COUNT-1:0] tx_st_sop;
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wire [SEG_COUNT-1:0] tx_st_eop;
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wire [SEG_COUNT-1:0] tx_st_valid;
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wire tx_st_ready;
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wire [SEG_COUNT-1:0] tx_st_err;
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wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr;
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wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx;
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wire [11:0] rx_buffer_limit;
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wire [1:0] rx_buffer_limit_tdm_idx;
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wire [15:0] tx_cdts_limit;
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wire [2:0] tx_cdts_limit_tdm_idx;
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wire [15:0] tl_cfg_ctl;
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wire [4:0] tl_cfg_add;
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wire [2:0] tl_cfg_func;
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pcie pcie_hip_inst (
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.p0_rx_st_ready_i(rx_st_ready),
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.p0_rx_st_sop_o(rx_st_sop),
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.p0_rx_st_eop_o(rx_st_eop),
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.p0_rx_st_data_o(rx_st_data),
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.p0_rx_st_valid_o(rx_st_valid),
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.p0_rx_st_empty_o(rx_st_empty),
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.p0_rx_st_hdr_o(rx_st_hdr),
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.p0_rx_st_tlp_prfx_o(rx_st_tlp_prfx),
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.p0_rx_st_bar_range_o(rx_st_bar_range),
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.p0_rx_st_tlp_abort_o(rx_st_tlp_abort),
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.p0_rx_par_err_o(),
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.p0_tx_st_sop_i(tx_st_sop),
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.p0_tx_st_eop_i(tx_st_eop),
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.p0_tx_st_data_i(tx_st_data),
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.p0_tx_st_valid_i(tx_st_valid),
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.p0_tx_st_err_i(tx_st_err),
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.p0_tx_st_ready_o(tx_st_ready),
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.p0_tx_st_hdr_i(tx_st_hdr),
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.p0_tx_st_tlp_prfx_i(tx_st_tlp_prfx),
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.p0_tx_par_err_o(),
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.p0_tx_cdts_limit_o(tx_cdts_limit),
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.p0_tx_cdts_limit_tdm_idx_o(tx_cdts_limit_tdm_idx),
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.p0_tl_cfg_func_o(tl_cfg_func),
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.p0_tl_cfg_add_o(tl_cfg_add),
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.p0_tl_cfg_ctl_o(tl_cfg_ctl),
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.p0_dl_timer_update_o(),
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.p0_reset_status_n(reset_status_n),
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.p0_pin_perst_n(),
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.p0_link_up_o(),
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.p0_dl_up_o(),
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.p0_surprise_down_err_o(),
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.p0_ltssm_state_o(),
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.rx_n_in0(pcie_rx_n[0]),
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.rx_n_in1(pcie_rx_n[1]),
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.rx_n_in2(pcie_rx_n[2]),
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.rx_n_in3(pcie_rx_n[3]),
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.rx_n_in4(pcie_rx_n[4]),
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.rx_n_in5(pcie_rx_n[5]),
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.rx_n_in6(pcie_rx_n[6]),
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.rx_n_in7(pcie_rx_n[7]),
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.rx_n_in8(pcie_rx_n[8]),
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.rx_n_in9(pcie_rx_n[9]),
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.rx_n_in10(pcie_rx_n[10]),
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.rx_n_in11(pcie_rx_n[11]),
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.rx_n_in12(pcie_rx_n[12]),
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.rx_n_in13(pcie_rx_n[13]),
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.rx_n_in14(pcie_rx_n[14]),
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.rx_n_in15(pcie_rx_n[15]),
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.rx_p_in0(pcie_rx_p[0]),
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.rx_p_in1(pcie_rx_p[1]),
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.rx_p_in2(pcie_rx_p[2]),
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.rx_p_in3(pcie_rx_p[3]),
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.rx_p_in4(pcie_rx_p[4]),
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.rx_p_in5(pcie_rx_p[5]),
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.rx_p_in6(pcie_rx_p[6]),
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.rx_p_in7(pcie_rx_p[7]),
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.rx_p_in8(pcie_rx_p[8]),
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.rx_p_in9(pcie_rx_p[9]),
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.rx_p_in10(pcie_rx_p[10]),
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.rx_p_in11(pcie_rx_p[11]),
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.rx_p_in12(pcie_rx_p[12]),
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.rx_p_in13(pcie_rx_p[13]),
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.rx_p_in14(pcie_rx_p[14]),
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.rx_p_in15(pcie_rx_p[15]),
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.tx_n_out0(pcie_tx_n[0]),
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.tx_n_out1(pcie_tx_n[1]),
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.tx_n_out2(pcie_tx_n[2]),
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.tx_n_out3(pcie_tx_n[3]),
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.tx_n_out4(pcie_tx_n[4]),
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.tx_n_out5(pcie_tx_n[5]),
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.tx_n_out6(pcie_tx_n[6]),
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.tx_n_out7(pcie_tx_n[7]),
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.tx_n_out8(pcie_tx_n[8]),
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.tx_n_out9(pcie_tx_n[9]),
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.tx_n_out10(pcie_tx_n[10]),
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.tx_n_out11(pcie_tx_n[11]),
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.tx_n_out12(pcie_tx_n[12]),
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.tx_n_out13(pcie_tx_n[13]),
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.tx_n_out14(pcie_tx_n[14]),
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.tx_n_out15(pcie_tx_n[15]),
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.tx_p_out0(pcie_tx_p[0]),
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.tx_p_out1(pcie_tx_p[1]),
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.tx_p_out2(pcie_tx_p[2]),
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.tx_p_out3(pcie_tx_p[3]),
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.tx_p_out4(pcie_tx_p[4]),
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.tx_p_out5(pcie_tx_p[5]),
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.tx_p_out6(pcie_tx_p[6]),
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.tx_p_out7(pcie_tx_p[7]),
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.tx_p_out8(pcie_tx_p[8]),
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.tx_p_out9(pcie_tx_p[9]),
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.tx_p_out10(pcie_tx_p[10]),
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.tx_p_out11(pcie_tx_p[11]),
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.tx_p_out12(pcie_tx_p[12]),
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.tx_p_out13(pcie_tx_p[13]),
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.tx_p_out14(pcie_tx_p[14]),
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.tx_p_out15(pcie_tx_p[15]),
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.coreclkout_hip(coreclkout_hip),
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.refclk0(pcie_refclk_p[0]),
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.refclk1(pcie_refclk_p[1]),
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.pin_perst_n(pcie_perst_n),
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.ninit_done(ninit_done)
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);
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fpga_core #(
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.SEG_COUNT(SEG_COUNT),
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.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
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.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
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.SEG_HDR_WIDTH(SEG_HDR_WIDTH),
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.SEG_PRFX_WIDTH(SEG_PRFX_WIDTH),
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.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
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.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
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.BAR0_APERTURE(BAR0_APERTURE),
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.BAR2_APERTURE(BAR2_APERTURE),
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.BAR4_APERTURE(BAR4_APERTURE)
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)
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fpga_core_inst (
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.clk(clk),
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.rst(rst),
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/*
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* GPIO
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*/
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.button(button),
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.sw(sw),
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.led(led),
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.led_bracket(led_bracket),
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/*
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* P-Tile RX AVST interface
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*/
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.rx_st_data(rx_st_data),
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.rx_st_empty(rx_st_empty),
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.rx_st_sop(rx_st_sop),
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.rx_st_eop(rx_st_eop),
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.rx_st_valid(rx_st_valid),
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.rx_st_ready(rx_st_ready),
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.rx_st_hdr(rx_st_hdr),
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.rx_st_tlp_prfx(rx_st_tlp_prfx),
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.rx_st_vf_active(rx_st_vf_active),
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.rx_st_func_num(rx_st_func_num),
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.rx_st_vf_num(rx_st_vf_num),
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.rx_st_bar_range(rx_st_bar_range),
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.rx_st_tlp_abort(rx_st_tlp_abort),
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.tx_st_data(tx_st_data),
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.tx_st_sop(tx_st_sop),
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.tx_st_eop(tx_st_eop),
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.tx_st_valid(tx_st_valid),
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.tx_st_ready(tx_st_ready),
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.tx_st_err(tx_st_err),
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.tx_st_hdr(tx_st_hdr),
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.tx_st_tlp_prfx(tx_st_tlp_prfx),
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.rx_buffer_limit(rx_buffer_limit),
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.rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx),
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.tx_cdts_limit(tx_cdts_limit),
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.tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx),
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.tl_cfg_ctl(tl_cfg_ctl),
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.tl_cfg_add(tl_cfg_add),
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.tl_cfg_func(tl_cfg_func)
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);
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endmodule
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`resetall
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