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https://github.com/corundum/corundum.git
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352 lines
12 KiB
Python
Executable File
352 lines
12 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Generates an Ethernet demux with the specified number of ports
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"""
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from __future__ import print_function
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import argparse
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import math
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from jinja2 import Template
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def main():
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parser = argparse.ArgumentParser(description=__doc__.strip())
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parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
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parser.add_argument('-n', '--name', type=str, help="module name")
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parser.add_argument('-o', '--output', type=str, help="output file name")
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args = parser.parse_args()
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try:
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generate(**args.__dict__)
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except IOError as ex:
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print(ex)
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exit(1)
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def generate(ports=4, name=None, output=None):
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if name is None:
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name = "eth_demux_64_{0}".format(ports)
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if output is None:
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output = name + ".v"
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print("Opening file '{0}'...".format(output))
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output_file = open(output, 'w')
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print("Generating {0} port Ethernet demux {1}...".format(ports, name))
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select_width = int(math.ceil(math.log(ports, 2)))
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t = Template(u"""/*
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Copyright (c) 2014-2016 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Ethernet {{n}} port demultiplexer (64 bit datapath)
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*/
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module {{name}}
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame input
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*/
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input wire input_eth_hdr_valid,
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output wire input_eth_hdr_ready,
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input wire [47:0] input_eth_dest_mac,
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input wire [47:0] input_eth_src_mac,
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input wire [15:0] input_eth_type,
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input wire [63:0] input_eth_payload_tdata,
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input wire [7:0] input_eth_payload_tkeep,
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input wire input_eth_payload_tvalid,
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output wire input_eth_payload_tready,
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input wire input_eth_payload_tlast,
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input wire input_eth_payload_tuser,
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/*
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* Ethernet frame outputs
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*/
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{%- for p in ports %}
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output wire output_{{p}}_eth_hdr_valid,
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input wire output_{{p}}_eth_hdr_ready,
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output wire [47:0] output_{{p}}_eth_dest_mac,
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output wire [47:0] output_{{p}}_eth_src_mac,
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output wire [15:0] output_{{p}}_eth_type,
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output wire [63:0] output_{{p}}_eth_payload_tdata,
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output wire [7:0] output_{{p}}_eth_payload_tkeep,
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output wire output_{{p}}_eth_payload_tvalid,
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input wire output_{{p}}_eth_payload_tready,
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output wire output_{{p}}_eth_payload_tlast,
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output wire output_{{p}}_eth_payload_tuser,
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{% endfor %}
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/*
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* Control
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*/
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input wire enable,
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input wire [{{w-1}}:0] select
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);
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reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
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reg frame_reg = 1'b0, frame_next;
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reg input_eth_hdr_ready_reg = 1'b0, input_eth_hdr_ready_next;
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reg input_eth_payload_tready_reg = 1'b0, input_eth_payload_tready_next;
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{% for p in ports %}
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reg output_{{p}}_eth_hdr_valid_reg = 1'b0, output_{{p}}_eth_hdr_valid_next;
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{%- endfor %}
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reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
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reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
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reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
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// internal datapath
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reg [63:0] output_eth_payload_tdata_int;
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reg [7:0] output_eth_payload_tkeep_int;
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reg output_eth_payload_tvalid_int;
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reg output_eth_payload_tready_int_reg = 1'b0;
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reg output_eth_payload_tlast_int;
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reg output_eth_payload_tuser_int;
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wire output_eth_payload_tready_int_early;
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assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
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assign input_eth_payload_tready = input_eth_payload_tready_reg;
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{% for p in ports %}
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assign output_{{p}}_eth_hdr_valid = output_{{p}}_eth_hdr_valid_reg;
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assign output_{{p}}_eth_dest_mac = output_eth_dest_mac_reg;
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assign output_{{p}}_eth_src_mac = output_eth_src_mac_reg;
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assign output_{{p}}_eth_type = output_eth_type_reg;
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{% endfor %}
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// mux for output control signals
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reg current_output_eth_hdr_valid;
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reg current_output_eth_hdr_ready;
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reg current_output_tvalid;
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reg current_output_tready;
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always @* begin
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case (select_reg)
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{%- for p in ports %}
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{{w}}'d{{p}}: begin
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current_output_eth_hdr_valid = output_{{p}}_eth_hdr_valid;
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current_output_eth_hdr_ready = output_{{p}}_eth_hdr_ready;
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current_output_tvalid = output_{{p}}_eth_payload_tvalid;
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current_output_tready = output_{{p}}_eth_payload_tready;
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end
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{%- endfor %}
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default: begin
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current_output_eth_hdr_valid = 1'b0;
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current_output_eth_hdr_ready = 1'b0;
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current_output_tvalid = 1'b0;
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current_output_tready = 1'b0;
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end
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endcase
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end
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always @* begin
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select_next = select_reg;
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frame_next = frame_reg;
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input_eth_hdr_ready_next = input_eth_hdr_ready_reg & ~input_eth_hdr_valid;
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input_eth_payload_tready_next = 1'b0;
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{%- for p in ports %}
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output_{{p}}_eth_hdr_valid_next = output_{{p}}_eth_hdr_valid_reg & ~output_{{p}}_eth_hdr_ready;
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{%- endfor %}
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output_eth_dest_mac_next = output_eth_dest_mac_reg;
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output_eth_src_mac_next = output_eth_src_mac_reg;
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output_eth_type_next = output_eth_type_reg;
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if (frame_reg) begin
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if (input_eth_payload_tvalid & input_eth_payload_tready) begin
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// end of frame detection
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frame_next = ~input_eth_payload_tlast;
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end
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end else if (enable & input_eth_hdr_valid & ~current_output_eth_hdr_valid & ~current_output_tvalid) begin
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// start of frame, grab select value
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frame_next = 1'b1;
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select_next = select;
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input_eth_hdr_ready_next = 1'b1;
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case (select)
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{%- for p in ports %}
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{{w}}'d{{p}}: output_{{p}}_eth_hdr_valid_next = 1'b1;
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{%- endfor %}
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endcase
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output_eth_dest_mac_next = input_eth_dest_mac;
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output_eth_src_mac_next = input_eth_src_mac;
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output_eth_type_next = input_eth_type;
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end
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input_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
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output_eth_payload_tdata_int = input_eth_payload_tdata;
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output_eth_payload_tkeep_int = input_eth_payload_tkeep;
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output_eth_payload_tvalid_int = input_eth_payload_tvalid & input_eth_payload_tready;
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output_eth_payload_tlast_int = input_eth_payload_tlast;
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output_eth_payload_tuser_int = input_eth_payload_tuser;
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end
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always @(posedge clk) begin
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if (rst) begin
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select_reg <= {{w}}'d0;
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frame_reg <= 1'b0;
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input_eth_hdr_ready_reg <= 1'b0;
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input_eth_payload_tready_reg <= 1'b0;
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{%- for p in ports %}
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output_{{p}}_eth_hdr_valid_reg <= 1'b0;
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{%- endfor %}
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end else begin
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select_reg <= select_next;
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frame_reg <= frame_next;
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input_eth_hdr_ready_reg <= input_eth_hdr_ready_next;
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input_eth_payload_tready_reg <= input_eth_payload_tready_next;
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{%- for p in ports %}
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output_{{p}}_eth_hdr_valid_reg <= output_{{p}}_eth_hdr_valid_next;
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{%- endfor %}
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end
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output_eth_dest_mac_reg <= output_eth_dest_mac_next;
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output_eth_src_mac_reg <= output_eth_src_mac_next;
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output_eth_type_reg <= output_eth_type_next;
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end
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// output datapath logic
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reg [63:0] output_eth_payload_tdata_reg = 64'd0;
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reg [7:0] output_eth_payload_tkeep_reg = 8'd0;
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{%- for p in ports %}
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reg output_{{p}}_eth_payload_tvalid_reg = 1'b0, output_{{p}}_eth_payload_tvalid_next;
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{%- endfor %}
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reg output_eth_payload_tlast_reg = 1'b0;
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reg output_eth_payload_tuser_reg = 1'b0;
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reg [63:0] temp_eth_payload_tdata_reg = 64'd0;
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reg [7:0] temp_eth_payload_tkeep_reg = 8'd0;
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reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
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reg temp_eth_payload_tlast_reg = 1'b0;
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reg temp_eth_payload_tuser_reg = 1'b0;
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// datapath control
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reg store_eth_payload_int_to_output;
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reg store_eth_payload_int_to_temp;
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reg store_eth_payload_temp_to_output;
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{% for p in ports %}
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assign output_{{p}}_eth_payload_tdata = output_eth_payload_tdata_reg;
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assign output_{{p}}_eth_payload_tkeep = output_eth_payload_tkeep_reg;
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assign output_{{p}}_eth_payload_tvalid = output_{{p}}_eth_payload_tvalid_reg;
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assign output_{{p}}_eth_payload_tlast = output_eth_payload_tlast_reg;
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assign output_{{p}}_eth_payload_tuser = output_eth_payload_tuser_reg;
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{% endfor %}
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_eth_payload_tready_int_early = current_output_tready | (~temp_eth_payload_tvalid_reg & (~current_output_tvalid | ~output_eth_payload_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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{%- for p in ports %}
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output_{{p}}_eth_payload_tvalid_next = output_{{p}}_eth_payload_tvalid_reg;
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{%- endfor %}
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temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
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store_eth_payload_int_to_output = 1'b0;
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store_eth_payload_int_to_temp = 1'b0;
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store_eth_payload_temp_to_output = 1'b0;
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if (output_eth_payload_tready_int_reg) begin
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// input is ready
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if (current_output_tready | ~current_output_tvalid) begin
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// output is ready or currently not valid, transfer data to output
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{%- for p in ports %}
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output_{{p}}_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == {{w}}'d{{p}});
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{%- endfor %}
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store_eth_payload_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
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store_eth_payload_int_to_temp = 1'b1;
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end
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end else if (current_output_tready) begin
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// input is not ready, but output is ready
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{%- for p in ports %}
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output_{{p}}_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == {{w}}'d{{p}});
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{%- endfor %}
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temp_eth_payload_tvalid_next = 1'b0;
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store_eth_payload_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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{%- for p in ports %}
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output_{{p}}_eth_payload_tvalid_reg <= 1'b0;
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{%- endfor %}
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output_eth_payload_tready_int_reg <= 1'b0;
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temp_eth_payload_tvalid_reg <= 1'b0;
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end else begin
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{%- for p in ports %}
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output_{{p}}_eth_payload_tvalid_reg <= output_{{p}}_eth_payload_tvalid_next;
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{%- endfor %}
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output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
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temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
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end
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// datapath
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if (store_eth_payload_int_to_output) begin
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output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
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output_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
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output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
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output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
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end else if (store_eth_payload_temp_to_output) begin
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output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
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output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg;
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output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
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output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
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end
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if (store_eth_payload_int_to_temp) begin
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temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
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temp_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
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temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
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temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
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end
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end
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endmodule
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""")
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output_file.write(t.render(
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n=ports,
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w=select_width,
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name=name,
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ports=range(ports)
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))
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print("Done")
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if __name__ == "__main__":
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main()
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