FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
corundum/tb
History
Alex Forencich 6fb2eb6b4e Remove unnecessary delays from testbenches
2021-02-24 13:50:45 -08:00
..
dma_client_axis_sink
Remove unnecessary delays from testbenches
2021-02-24 13:50:45 -08:00
dma_client_axis_source
Add same-width test cases to DMA clients
2021-02-16 01:26:05 -08:00
dma_if_pcie_us
Remove unnecessary delays from testbenches
2021-02-24 13:50:45 -08:00
dma_if_pcie_us_rd
Remove unnecessary delays from testbenches
2021-02-24 13:50:45 -08:00
dma_if_pcie_us_wr
Update testbench
2021-02-12 16:59:13 -08:00
pcie_us_axi_dma
Rework sim_build output directory, fix default makefile target
2020-12-29 16:26:48 -08:00
pcie_us_axi_dma_rd
Rework sim_build output directory, fix default makefile target
2020-12-29 16:26:48 -08:00
pcie_us_axi_dma_wr
Rework sim_build output directory, fix default makefile target
2020-12-29 16:26:48 -08:00
pcie_us_axi_master
Rework sim_build output directory, fix default makefile target
2020-12-29 16:26:48 -08:00
pcie_us_axi_master_rd
Rework sim_build output directory, fix default makefile target
2020-12-29 16:26:48 -08:00
pcie_us_axi_master_wr
Rework sim_build output directory, fix default makefile target
2020-12-29 16:26:48 -08:00
pcie_us_axil_master
Rework sim_build output directory, fix default makefile target
2020-12-29 16:26:48 -08:00
axi.py
Update AXI simulation model
2020-07-02 21:28:35 -07:00
axil.py
Add Ultascale PCIe AXI lite master module and testbenches
2018-09-25 21:09:20 -07:00
axis_ep.py
Add AXI stream endpoint model
2018-09-25 20:55:44 -07:00
dma_psdp_ram.py
Add wr_done signal to RAM model and placeholders to DMA components
2021-02-24 13:47:53 -08:00
dma_ram.py
Add segmented DMA RAM simulation model
2019-10-08 15:14:32 -07:00
Makefile
Add cocotb testbenches
2020-12-19 14:10:57 -08:00
pcie_us.py
Placeholder values for flow control credit outputs
2019-12-06 19:16:05 -08:00
pcie_usp.py
Placeholder values for flow control credit outputs
2019-12-06 19:16:05 -08:00
pcie.py
Improve BAR initialization
2020-07-24 22:54:55 -07:00
test_dma_client_axis_sink_128_64.py
Update python parameter computation to match verilog clog2
2019-11-24 00:01:33 -08:00
test_dma_client_axis_sink_128_64.v
Add AXI stream sink DMA client module and testbench
2019-10-12 22:35:57 -07:00
test_dma_client_axis_sink_512_64.py
Update python parameter computation to match verilog clog2
2019-11-24 00:01:33 -08:00
test_dma_client_axis_sink_512_64.v
Add AXI stream sink DMA client module and testbench
2019-10-12 22:35:57 -07:00
test_dma_client_axis_source_128_64.py
Update python parameter computation to match verilog clog2
2019-11-24 00:01:33 -08:00
test_dma_client_axis_source_128_64.v
Add AXI stream source DMA client module and testbench
2019-10-12 22:34:15 -07:00
test_dma_client_axis_source_512_64.py
Update python parameter computation to match verilog clog2
2019-11-24 00:01:33 -08:00
test_dma_client_axis_source_512_64.v
Add AXI stream source DMA client module and testbench
2019-10-12 22:34:15 -07:00
test_dma_if_pcie_us_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_64.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_64.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_128.py
Remove extraneous character
2019-12-07 14:36:32 -08:00
test_dma_if_pcie_us_rd_128.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_512.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_512.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_64.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_64.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_128.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_128.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_512.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_512.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_tag_manager.py
Update parameters
2019-03-03 13:37:34 -08:00
test_pcie_tag_manager.v
Update parameters
2019-03-03 13:37:34 -08:00
test_pcie_us_axi_dma_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_64.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_64.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_128.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_128.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_512.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_512.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_64.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_64.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_128.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_128.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_512.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_512.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_master_64.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_64.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_128.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_128.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_256.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_256.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_64.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_64.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_128.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_128.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_256.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_256.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_512.py
Update AXI master modules to support 512 bit interface
2019-10-14 16:20:46 -07:00
test_pcie_us_axi_master_rd_512.v
Update AXI master modules to support 512 bit interface
2019-10-14 16:20:46 -07:00
test_pcie_us_axi_master_wr_64.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_64.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_128.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_128.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_256.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_256.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_512.py
Update AXI master modules to support 512 bit interface
2019-10-14 16:20:46 -07:00
test_pcie_us_axi_master_wr_512.v
Update AXI master modules to support 512 bit interface
2019-10-14 16:20:46 -07:00
test_pcie_us_axil_master_64.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie_us_axil_master_64.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axil_master_128.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie_us_axil_master_128.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axil_master_256.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie_us_axil_master_256.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axil_master_512.py
Update AXI lite master module to support 512 bit interface
2019-10-14 15:58:38 -07:00
test_pcie_us_axil_master_512.v
Update AXI lite master module to support 512 bit interface
2019-10-14 15:58:38 -07:00
test_pcie_us.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie_usp.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie.py
Don't use traceSignals
2019-07-14 21:45:10 -07:00