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132 lines
3.3 KiB
Verilog
132 lines
3.3 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for axil_ram
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*/
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module test_axil_ram;
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// Parameters
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parameter DATA_WIDTH = 32;
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parameter ADDR_WIDTH = 16;
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parameter STRB_WIDTH = DATA_WIDTH/8;
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parameter PIPELINE_OUTPUT = 0;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [ADDR_WIDTH-1:0] s_axil_awaddr = 0;
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reg [2:0] s_axil_awprot = 0;
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reg s_axil_awvalid = 0;
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reg [DATA_WIDTH-1:0] s_axil_wdata = 0;
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reg [STRB_WIDTH-1:0] s_axil_wstrb = 0;
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reg s_axil_wvalid = 0;
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reg s_axil_bready = 0;
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reg [ADDR_WIDTH-1:0] s_axil_araddr = 0;
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reg [2:0] s_axil_arprot = 0;
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reg s_axil_arvalid = 0;
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reg s_axil_rready = 0;
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// Outputs
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wire s_axil_awready;
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wire s_axil_wready;
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wire [1:0] s_axil_bresp;
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wire s_axil_bvalid;
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wire s_axil_arready;
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wire [DATA_WIDTH-1:0] s_axil_rdata;
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wire [1:0] s_axil_rresp;
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wire s_axil_rvalid;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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s_axil_awaddr,
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s_axil_awprot,
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s_axil_awvalid,
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s_axil_wdata,
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s_axil_wstrb,
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s_axil_wvalid,
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s_axil_bready,
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s_axil_araddr,
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s_axil_arprot,
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s_axil_arvalid,
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s_axil_rready
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);
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$to_myhdl(
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s_axil_awready,
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s_axil_wready,
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s_axil_bresp,
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s_axil_bvalid,
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s_axil_arready,
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s_axil_rdata,
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s_axil_rresp,
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s_axil_rvalid
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);
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// dump file
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$dumpfile("test_axil_ram.lxt");
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$dumpvars(0, test_axil_ram);
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end
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axil_ram #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.STRB_WIDTH(STRB_WIDTH),
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.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.s_axil_awaddr(s_axil_awaddr),
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.s_axil_awprot(s_axil_awprot),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awready(s_axil_awready),
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.s_axil_wdata(s_axil_wdata),
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.s_axil_wstrb(s_axil_wstrb),
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.s_axil_wvalid(s_axil_wvalid),
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.s_axil_wready(s_axil_wready),
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.s_axil_bresp(s_axil_bresp),
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.s_axil_bvalid(s_axil_bvalid),
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.s_axil_bready(s_axil_bready),
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.s_axil_araddr(s_axil_araddr),
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.s_axil_arprot(s_axil_arprot),
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.s_axil_arvalid(s_axil_arvalid),
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.s_axil_arready(s_axil_arready),
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.s_axil_rdata(s_axil_rdata),
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.s_axil_rresp(s_axil_rresp),
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.s_axil_rvalid(s_axil_rvalid),
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.s_axil_rready(s_axil_rready)
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);
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endmodule
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