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corundum/fpga/common/rtl
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Alex Forencich 941288e926 fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-12 17:12:23 -07:00
..
avst2axis.v
Only use avst_empty at end of frame
2022-07-22 23:00:09 -07:00
axis2avst.v
Add 25G mqnic design for DE10-Agilex
2022-07-19 23:43:22 -07:00
cmac_pad.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
cpl_op_mux.v
Pipeline arbitration delay in muxes
2022-05-15 19:35:39 -07:00
cpl_queue_manager.v
fpga/common: Add backpressure to completion queue manager event/interrupt output
2022-08-16 18:51:53 -07:00
cpl_write.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
desc_fetch.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
desc_op_mux.v
Pipeline arbitration delay in muxes
2022-05-15 19:35:39 -07:00
eth_xcvr_phy_10g_gty_quad_wrapper.v
Use PHY rx_status signal for link status detection
2022-05-17 00:46:05 -07:00
eth_xcvr_phy_10g_gty_wrapper.v
Use PHY rx_status signal for link status detection
2022-05-17 00:46:05 -07:00
event_mux.v
Pipeline arbitration delay in muxes
2022-05-15 19:35:39 -07:00
mac_ts_insert.v
Rename cmac_ts_insert to mac_ts_insert
2022-07-18 22:27:27 -07:00
mqnic_core_axi.v
fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section
2022-10-12 17:12:23 -07:00
mqnic_core_pcie_ptile.v
fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section
2022-10-12 17:12:23 -07:00
mqnic_core_pcie_s10.v
fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section
2022-10-12 17:12:23 -07:00
mqnic_core_pcie_us.v
fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section
2022-10-12 17:12:23 -07:00
mqnic_core_pcie.v
fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section
2022-10-12 17:12:23 -07:00
mqnic_core.v
fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section
2022-10-12 17:12:23 -07:00
mqnic_egress.v
Initial implementation of shared interface datapath
2021-12-31 14:33:31 -08:00
mqnic_ingress.v
Add RX queue mapping module
2022-04-23 00:12:22 -07:00
mqnic_interface_rx.v
fpga/common: Clean up parameters
2022-09-21 15:19:49 -07:00
mqnic_interface_tx.v
fpga/common: Clean up parameters
2022-09-21 15:19:49 -07:00
mqnic_interface.v
fpga/common: Use correct parameter
2022-10-06 21:15:26 -07:00
mqnic_l2_egress.v
Add layer 2 ingress/egress modules
2022-02-13 23:09:41 -08:00
mqnic_l2_ingress.v
Add layer 2 ingress/egress modules
2022-02-13 23:09:41 -08:00
mqnic_port_map_mac_axis.v
Add TX PTP clock to port map module
2022-07-18 22:25:39 -07:00
mqnic_port_map_phy_xgmii.v
Add port register blocks with support for PHY link status reporting
2022-05-04 09:03:37 -07:00
mqnic_port_rx.v
Decouple transmit completion handling from PTP timestamping
2022-05-01 17:41:47 -07:00
mqnic_port_tx.v
Add port register blocks with support for PHY link status reporting
2022-05-04 09:03:37 -07:00
mqnic_port.v
Add port register blocks with support for PHY link status reporting
2022-05-04 09:03:37 -07:00
mqnic_ptp_clock.v
Add stretched PTP PPS output
2022-07-18 22:25:58 -07:00
mqnic_ptp_perout.v
Register space reorganization
2021-12-29 22:31:46 -08:00
mqnic_ptp.v
Add stretched PTP PPS output
2022-07-18 22:25:58 -07:00
mqnic_rx_queue_map.v
Add RX queue mapping module
2022-04-23 00:12:22 -07:00
mqnic_tx_scheduler_block_rr_tdma.v
Add port register blocks with support for PHY link status reporting
2022-05-04 09:03:37 -07:00
mqnic_tx_scheduler_block_rr.v
Add port register blocks with support for PHY link status reporting
2022-05-04 09:03:37 -07:00
queue_manager.v
fix partial initialisation of memory
2022-03-24 15:50:25 -07:00
rb_drp.v
Add DRP register block
2022-02-21 23:20:54 -08:00
rx_checksum.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
rx_engine.v
fpga/common: Clean up parameters
2022-09-21 15:19:49 -07:00
rx_fifo.v
Add missing parameter connection in rx_fifo
2022-01-26 09:44:35 -08:00
rx_hash.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
stats_collect.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
stats_counter.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
stats_dma_if_axi.v
fpga/mqnic: Clean up PCIe DMA IF flow control connections
2022-08-03 23:04:05 -07:00
stats_dma_if_pcie.v
fpga/mqnic: Clean up PCIe DMA IF flow control connections
2022-08-03 23:04:05 -07:00
stats_dma_latency.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
stats_pcie_if.v
Update PCIe TLP interface parametrization
2022-06-05 14:31:10 -07:00
stats_pcie_tlp.v
Update PCIe TLP interface parametrization
2022-06-05 14:31:10 -07:00
tdma_ber_ch.v
Fix TDMA BER pipeline register
2022-03-17 13:28:41 -07:00
tdma_ber.v
Add pipeline registers to TDMA BER modules
2022-03-15 17:40:27 -07:00
tdma_scheduler.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tx_checksum.v
Rewrite early ready condition
2022-05-15 19:32:28 -07:00
tx_engine.v
fpga/common: Fix lost TX request status issue in transmit engine
2022-09-21 15:20:27 -07:00
tx_fifo.v
Initial implementation of shared interface datapath
2021-12-31 14:33:31 -08:00
tx_req_mux.v
Pipeline arbitration delay in muxes
2022-05-15 19:35:39 -07:00
tx_scheduler_ctrl_tdma.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tx_scheduler_rr.v
fix partial initialisation of memory
2022-03-24 15:50:25 -07:00