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88 lines
3.0 KiB
Verilog
88 lines
3.0 KiB
Verilog
/*
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Copyright 2022, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* NIC layer 2 egress processing
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*/
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module mqnic_l2_egress #
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(
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = 256,
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
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// AXI stream tuser signal width
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parameter AXIS_USER_WIDTH = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Transmit data input
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*/
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser,
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/*
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* Transmit data output
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*/
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser
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);
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// placeholder
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assign m_axis_tdata = s_axis_tdata;
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assign m_axis_tkeep = s_axis_tkeep;
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assign m_axis_tvalid = s_axis_tvalid;
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assign s_axis_tready = m_axis_tready;
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assign m_axis_tlast = s_axis_tlast;
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assign m_axis_tuser = s_axis_tuser;
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endmodule
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`resetall
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