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247 lines
8.1 KiB
Verilog
247 lines
8.1 KiB
Verilog
/*
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Copyright 2021, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* TX FIFO
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*/
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module tx_fifo #
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(
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// FIFO depth in words (each FIFO)
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// KEEP_WIDTH words per cycle if KEEP_ENABLE set
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// Rounded up to nearest power of 2 cycles
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parameter FIFO_DEPTH = 4096,
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// Number of AXI stream outputs
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parameter PORTS = 4,
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// Width of input AXI stream interfaces in bits
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parameter S_DATA_WIDTH = 8,
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// Propagate tkeep signal
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parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
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// tkeep signal width (words per cycle)
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parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
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// Width of output AXI stream interfaces in bits
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parameter M_DATA_WIDTH = 8,
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// Propagate tkeep signal
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parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
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// tkeep signal width (words per cycle)
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parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
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// Propagate tid signal
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parameter ID_ENABLE = 0,
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// tid signal width
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parameter ID_WIDTH = 8,
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// output tdest signal width
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parameter M_DEST_WIDTH = 3,
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// input tdest signal width
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// must be wide enough to uniquely address outputs
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parameter S_DEST_WIDTH = M_DEST_WIDTH+$clog2(PORTS),
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// Propagate tuser signal
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parameter USER_ENABLE = 1,
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// tuser signal width
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parameter USER_WIDTH = 1,
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// number of RAM pipeline registers
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parameter RAM_PIPELINE = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI Stream input
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*/
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input wire [S_DATA_WIDTH-1:0] s_axis_tdata,
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input wire [S_KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [ID_WIDTH-1:0] s_axis_tid,
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input wire [S_DEST_WIDTH-1:0] s_axis_tdest,
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input wire [USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI Stream outputs
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*/
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output wire [PORTS*M_DATA_WIDTH-1:0] m_axis_tdata,
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output wire [PORTS*M_KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire [PORTS-1:0] m_axis_tvalid,
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input wire [PORTS-1:0] m_axis_tready,
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output wire [PORTS-1:0] m_axis_tlast,
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output wire [PORTS*ID_WIDTH-1:0] m_axis_tid,
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output wire [PORTS*M_DEST_WIDTH-1:0] m_axis_tdest,
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output wire [PORTS*USER_WIDTH-1:0] m_axis_tuser,
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/*
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* Status
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*/
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output wire [PORTS-1:0] status_overflow,
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output wire [PORTS-1:0] status_bad_frame,
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output wire [PORTS-1:0] status_good_frame
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);
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wire [PORTS*S_DATA_WIDTH-1:0] axis_fifo_tdata;
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wire [PORTS*S_KEEP_WIDTH-1:0] axis_fifo_tkeep;
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wire [PORTS-1:0] axis_fifo_tvalid;
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wire [PORTS-1:0] axis_fifo_tready;
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wire [PORTS-1:0] axis_fifo_tlast;
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wire [PORTS*ID_WIDTH-1:0] axis_fifo_tid;
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wire [PORTS*M_DEST_WIDTH-1:0] axis_fifo_tdest;
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wire [PORTS*USER_WIDTH-1:0] axis_fifo_tuser;
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generate
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genvar n;
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if (PORTS > 1) begin : demux
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axis_demux #(
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.M_COUNT(PORTS),
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.DATA_WIDTH(S_DATA_WIDTH),
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.KEEP_ENABLE(S_KEEP_ENABLE),
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.KEEP_WIDTH(S_KEEP_WIDTH),
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.ID_ENABLE(ID_ENABLE),
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.ID_WIDTH(ID_WIDTH),
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.DEST_ENABLE(1),
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.S_DEST_WIDTH(S_DEST_WIDTH),
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.M_DEST_WIDTH(M_DEST_WIDTH),
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.USER_ENABLE(USER_ENABLE),
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.USER_WIDTH(USER_WIDTH),
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.TDEST_ROUTE(1)
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)
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switch_inst (
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.clk(clk),
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.rst(rst),
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// AXI Stream input
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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.s_axis_tid(s_axis_tid),
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.s_axis_tdest(s_axis_tdest),
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.s_axis_tuser(s_axis_tuser),
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// AXI Stream outputs
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.m_axis_tdata(axis_fifo_tdata),
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.m_axis_tkeep(axis_fifo_tkeep),
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.m_axis_tvalid(axis_fifo_tvalid),
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.m_axis_tready(axis_fifo_tready),
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.m_axis_tlast(axis_fifo_tlast),
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.m_axis_tid(axis_fifo_tid),
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.m_axis_tdest(axis_fifo_tdest),
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.m_axis_tuser(axis_fifo_tuser),
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// Control
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.enable(1),
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.drop(0),
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.select(0)
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);
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end else begin
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assign axis_fifo_tdata = s_axis_tdata;
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assign axis_fifo_tkeep = s_axis_tkeep;
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assign axis_fifo_tvalid = s_axis_tvalid;
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assign s_axis_tready = axis_fifo_tready;
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assign axis_fifo_tlast = s_axis_tlast;
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assign axis_fifo_tid = s_axis_tid;
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assign axis_fifo_tdest = s_axis_tdest;
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assign axis_fifo_tuser = s_axis_tuser;
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end
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for (n = 0; n < PORTS; n = n + 1) begin : fifo
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axis_fifo_adapter #(
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.DEPTH(FIFO_DEPTH),
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.S_DATA_WIDTH(S_DATA_WIDTH),
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.S_KEEP_ENABLE(S_KEEP_ENABLE),
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.S_KEEP_WIDTH(S_KEEP_WIDTH),
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.M_DATA_WIDTH(M_DATA_WIDTH),
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.M_KEEP_ENABLE(M_KEEP_ENABLE),
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.M_KEEP_WIDTH(M_KEEP_WIDTH),
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.ID_ENABLE(ID_ENABLE),
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.ID_WIDTH(ID_WIDTH),
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.DEST_ENABLE(1),
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.DEST_WIDTH(M_DEST_WIDTH),
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.USER_ENABLE(USER_ENABLE),
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.USER_WIDTH(USER_WIDTH),
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.RAM_PIPELINE(RAM_PIPELINE),
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.FRAME_FIFO(1),
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.USER_BAD_FRAME_VALUE(1'b1),
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.USER_BAD_FRAME_MASK(1'b1),
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.DROP_BAD_FRAME(USER_ENABLE),
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.DROP_WHEN_FULL(0)
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)
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fifo_inst (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(axis_fifo_tdata[n*S_DATA_WIDTH +: S_DATA_WIDTH]),
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.s_axis_tkeep(axis_fifo_tkeep[n*S_KEEP_WIDTH +: S_KEEP_WIDTH]),
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.s_axis_tvalid(axis_fifo_tvalid[n +: 1]),
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.s_axis_tready(axis_fifo_tready[n +: 1]),
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.s_axis_tlast(axis_fifo_tlast[n +: 1]),
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.s_axis_tid(axis_fifo_tid[n*ID_WIDTH +: ID_WIDTH]),
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.s_axis_tdest(axis_fifo_tdest[n*M_DEST_WIDTH +: M_DEST_WIDTH]),
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.s_axis_tuser(axis_fifo_tuser[n*USER_WIDTH +: USER_WIDTH]),
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// AXI output
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.m_axis_tdata(m_axis_tdata[n*M_DATA_WIDTH +: M_DATA_WIDTH]),
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.m_axis_tkeep(m_axis_tkeep[n*M_KEEP_WIDTH +: M_KEEP_WIDTH]),
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.m_axis_tvalid(m_axis_tvalid[n +: 1]),
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.m_axis_tready(m_axis_tready[n +: 1]),
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.m_axis_tlast(m_axis_tlast[n +: 1]),
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.m_axis_tid(m_axis_tid[n*ID_WIDTH +: ID_WIDTH]),
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.m_axis_tdest(m_axis_tdest[n*M_DEST_WIDTH +: M_DEST_WIDTH]),
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.m_axis_tuser(m_axis_tuser[n*USER_WIDTH +: USER_WIDTH]),
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// Status
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.status_overflow(status_overflow),
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.status_bad_frame(status_bad_frame),
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.status_good_frame(status_good_frame)
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);
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end
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endgenerate
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endmodule
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`resetall
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