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408 lines
13 KiB
Verilog
408 lines
13 KiB
Verilog
/*
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* GPIO
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*/
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output wire hbm_cattrip,
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/*
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* PCI express
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*/
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input wire [15:0] pcie_rx_p,
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input wire [15:0] pcie_rx_n,
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output wire [15:0] pcie_tx_p,
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output wire [15:0] pcie_tx_n,
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input wire pcie_refclk_1_p,
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input wire pcie_refclk_1_n,
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input wire pcie_reset_n
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);
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parameter AXIS_PCIE_DATA_WIDTH = 512;
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parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
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parameter AXIS_PCIE_RC_USER_WIDTH = 161;
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parameter AXIS_PCIE_RQ_USER_WIDTH = 137;
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parameter AXIS_PCIE_CQ_USER_WIDTH = 183;
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parameter AXIS_PCIE_CC_USER_WIDTH = 81;
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// Clock and reset
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wire pcie_user_clk;
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wire pcie_user_reset;
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// GPIO
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assign hbm_cattrip = 1'b0;
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// PCIe
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wire pcie_sys_clk;
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wire pcie_sys_clk_gt;
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IBUFDS_GTE4 #(
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.REFCLK_HROW_CK_SEL(2'b00)
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)
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ibufds_gte4_pcie_mgt_refclk_inst (
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.I (pcie_refclk_1_p),
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.IB (pcie_refclk_1_n),
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.CEB (1'b0),
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.O (pcie_sys_clk_gt),
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.ODIV2 (pcie_sys_clk)
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);
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wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata;
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wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep;
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wire axis_rq_tlast;
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wire axis_rq_tready;
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wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
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wire axis_rq_tvalid;
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wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata;
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wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep;
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wire axis_rc_tlast;
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wire axis_rc_tready;
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wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
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wire axis_rc_tvalid;
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wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata;
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wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep;
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wire axis_cq_tlast;
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wire axis_cq_tready;
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wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
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wire axis_cq_tvalid;
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wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata;
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wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep;
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wire axis_cc_tlast;
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wire axis_cc_tready;
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wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
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wire axis_cc_tvalid;
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// ila_0 rq_ila (
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// .clk(pcie_user_clk),
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// .probe0(axis_rq_tdata),
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// .probe1(axis_rq_tkeep),
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// .probe2(axis_rq_tlast),
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// .probe3(axis_rq_tready),
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// .probe4(axis_rq_tuser),
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// .probe5(axis_rq_tvalid)
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// );
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// ila_0 rc_ila (
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// .clk(pcie_user_clk),
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// .probe0(axis_rc_tdata),
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// .probe1(axis_rc_tkeep),
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// .probe2(axis_rc_tlast),
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// .probe3(axis_rc_tready),
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// .probe4(axis_rc_tuser),
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// .probe5(axis_rc_tvalid)
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// );
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wire [2:0] cfg_max_payload;
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wire [2:0] cfg_max_read_req;
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wire [9:0] cfg_mgmt_addr;
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wire [7:0] cfg_mgmt_function_number;
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wire cfg_mgmt_write;
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wire [31:0] cfg_mgmt_write_data;
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wire [3:0] cfg_mgmt_byte_enable;
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wire cfg_mgmt_read;
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wire [31:0] cfg_mgmt_read_data;
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wire cfg_mgmt_read_write_done;
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wire [3:0] cfg_interrupt_msi_enable;
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wire [11:0] cfg_interrupt_msi_mmenable;
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wire cfg_interrupt_msi_mask_update;
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wire [31:0] cfg_interrupt_msi_data;
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wire [3:0] cfg_interrupt_msi_select;
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wire [31:0] cfg_interrupt_msi_int;
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wire [31:0] cfg_interrupt_msi_pending_status;
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wire cfg_interrupt_msi_pending_status_data_enable;
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wire [3:0] cfg_interrupt_msi_pending_status_function_num;
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wire cfg_interrupt_msi_sent;
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wire cfg_interrupt_msi_fail;
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wire [2:0] cfg_interrupt_msi_attr;
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wire cfg_interrupt_msi_tph_present;
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wire [1:0] cfg_interrupt_msi_tph_type;
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wire [8:0] cfg_interrupt_msi_tph_st_tag;
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wire [3:0] cfg_interrupt_msi_function_number;
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wire status_error_cor;
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wire status_error_uncor;
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pcie4c_uscale_plus_0
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pcie4c_uscale_plus_inst (
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.pci_exp_txn(pcie_tx_n),
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.pci_exp_txp(pcie_tx_p),
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.pci_exp_rxn(pcie_rx_n),
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.pci_exp_rxp(pcie_rx_p),
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.user_clk(pcie_user_clk),
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.user_reset(pcie_user_reset),
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.user_lnk_up(),
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.s_axis_rq_tdata(axis_rq_tdata),
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.s_axis_rq_tkeep(axis_rq_tkeep),
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.s_axis_rq_tlast(axis_rq_tlast),
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.s_axis_rq_tready(axis_rq_tready),
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.s_axis_rq_tuser(axis_rq_tuser),
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.s_axis_rq_tvalid(axis_rq_tvalid),
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.m_axis_rc_tdata(axis_rc_tdata),
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.m_axis_rc_tkeep(axis_rc_tkeep),
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.m_axis_rc_tlast(axis_rc_tlast),
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.m_axis_rc_tready(axis_rc_tready),
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.m_axis_rc_tuser(axis_rc_tuser),
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.m_axis_rc_tvalid(axis_rc_tvalid),
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.m_axis_cq_tdata(axis_cq_tdata),
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.m_axis_cq_tkeep(axis_cq_tkeep),
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.m_axis_cq_tlast(axis_cq_tlast),
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.m_axis_cq_tready(axis_cq_tready),
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.m_axis_cq_tuser(axis_cq_tuser),
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.m_axis_cq_tvalid(axis_cq_tvalid),
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.s_axis_cc_tdata(axis_cc_tdata),
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.s_axis_cc_tkeep(axis_cc_tkeep),
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.s_axis_cc_tlast(axis_cc_tlast),
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.s_axis_cc_tready(axis_cc_tready),
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.s_axis_cc_tuser(axis_cc_tuser),
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.s_axis_cc_tvalid(axis_cc_tvalid),
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.pcie_rq_seq_num0(),
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.pcie_rq_seq_num_vld0(),
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.pcie_rq_seq_num1(),
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.pcie_rq_seq_num_vld1(),
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.pcie_rq_tag0(),
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.pcie_rq_tag1(),
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.pcie_rq_tag_av(),
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.pcie_rq_tag_vld0(),
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.pcie_rq_tag_vld1(),
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.pcie_tfc_nph_av(),
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.pcie_tfc_npd_av(),
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.pcie_cq_np_req(1'b1),
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.pcie_cq_np_req_count(),
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.cfg_phy_link_down(),
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.cfg_phy_link_status(),
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.cfg_negotiated_width(),
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.cfg_current_speed(),
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.cfg_max_payload(cfg_max_payload),
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.cfg_max_read_req(cfg_max_read_req),
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.cfg_function_status(),
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.cfg_function_power_state(),
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.cfg_vf_status(),
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.cfg_vf_power_state(),
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.cfg_link_power_state(),
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.cfg_mgmt_addr(cfg_mgmt_addr),
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.cfg_mgmt_function_number(cfg_mgmt_function_number),
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.cfg_mgmt_write(cfg_mgmt_write),
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.cfg_mgmt_write_data(cfg_mgmt_write_data),
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.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
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.cfg_mgmt_read(cfg_mgmt_read),
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.cfg_mgmt_read_data(cfg_mgmt_read_data),
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.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
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.cfg_mgmt_debug_access(1'b0),
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.cfg_err_cor_out(),
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.cfg_err_nonfatal_out(),
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.cfg_err_fatal_out(),
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.cfg_local_error_valid(),
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.cfg_local_error_out(),
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.cfg_ltssm_state(),
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.cfg_rx_pm_state(),
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.cfg_tx_pm_state(),
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.cfg_rcb_status(),
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.cfg_obff_enable(),
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.cfg_pl_status_change(),
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.cfg_tph_requester_enable(),
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.cfg_tph_st_mode(),
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.cfg_vf_tph_requester_enable(),
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.cfg_vf_tph_st_mode(),
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.cfg_msg_received(),
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.cfg_msg_received_data(),
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.cfg_msg_received_type(),
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.cfg_msg_transmit(1'b0),
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.cfg_msg_transmit_type(3'd0),
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.cfg_msg_transmit_data(32'd0),
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.cfg_msg_transmit_done(),
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.cfg_fc_ph(),
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.cfg_fc_pd(),
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.cfg_fc_nph(),
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.cfg_fc_npd(),
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.cfg_fc_cplh(),
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.cfg_fc_cpld(),
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.cfg_fc_sel(3'd0),
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.cfg_dsn(64'd0),
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.cfg_bus_number(),
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.cfg_power_state_change_ack(1'b1),
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.cfg_power_state_change_interrupt(),
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.cfg_err_cor_in(status_error_cor),
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.cfg_err_uncor_in(status_error_uncor),
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.cfg_flr_in_process(),
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.cfg_flr_done(4'd0),
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.cfg_vf_flr_in_process(),
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.cfg_vf_flr_func_num(8'd0),
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.cfg_vf_flr_done(8'd0),
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.cfg_link_training_enable(1'b1),
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.cfg_interrupt_int(4'd0),
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.cfg_interrupt_pending(4'd0),
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.cfg_interrupt_sent(),
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.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
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.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
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.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
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.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
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.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
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.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
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.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
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.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
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.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
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.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
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.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
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.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
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.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
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.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
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.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
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.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
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.cfg_pm_aspm_l1_entry_reject(1'b0),
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.cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
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.cfg_hot_reset_out(),
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.cfg_config_space_enable(1'b1),
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.cfg_req_pm_transition_l23_ready(1'b0),
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.cfg_hot_reset_in(1'b0),
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.cfg_ds_port_number(8'd0),
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.cfg_ds_bus_number(8'd0),
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.cfg_ds_device_number(5'd0),
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.sys_clk(pcie_sys_clk),
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.sys_clk_gt(pcie_sys_clk_gt),
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.sys_reset(pcie_reset_n),
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.phy_rdy_out()
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);
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fpga_core #(
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.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
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.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
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.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
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.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
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.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
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.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH)
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)
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core_inst (
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/*
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* Clock: 250 MHz
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* Synchronous reset
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*/
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.clk(pcie_user_clk),
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.rst(pcie_user_reset),
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/*
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* PCIe
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*/
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.m_axis_rq_tdata(axis_rq_tdata),
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.m_axis_rq_tkeep(axis_rq_tkeep),
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.m_axis_rq_tlast(axis_rq_tlast),
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.m_axis_rq_tready(axis_rq_tready),
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.m_axis_rq_tuser(axis_rq_tuser),
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.m_axis_rq_tvalid(axis_rq_tvalid),
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.s_axis_rc_tdata(axis_rc_tdata),
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.s_axis_rc_tkeep(axis_rc_tkeep),
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.s_axis_rc_tlast(axis_rc_tlast),
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.s_axis_rc_tready(axis_rc_tready),
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.s_axis_rc_tuser(axis_rc_tuser),
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.s_axis_rc_tvalid(axis_rc_tvalid),
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.s_axis_cq_tdata(axis_cq_tdata),
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.s_axis_cq_tkeep(axis_cq_tkeep),
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.s_axis_cq_tlast(axis_cq_tlast),
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.s_axis_cq_tready(axis_cq_tready),
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.s_axis_cq_tuser(axis_cq_tuser),
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.s_axis_cq_tvalid(axis_cq_tvalid),
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.m_axis_cc_tdata(axis_cc_tdata),
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.m_axis_cc_tkeep(axis_cc_tkeep),
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.m_axis_cc_tlast(axis_cc_tlast),
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.m_axis_cc_tready(axis_cc_tready),
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.m_axis_cc_tuser(axis_cc_tuser),
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.m_axis_cc_tvalid(axis_cc_tvalid),
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.cfg_max_payload(cfg_max_payload),
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.cfg_max_read_req(cfg_max_read_req),
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.cfg_mgmt_addr(cfg_mgmt_addr),
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.cfg_mgmt_function_number(cfg_mgmt_function_number),
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.cfg_mgmt_write(cfg_mgmt_write),
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.cfg_mgmt_write_data(cfg_mgmt_write_data),
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.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
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.cfg_mgmt_read(cfg_mgmt_read),
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.cfg_mgmt_read_data(cfg_mgmt_read_data),
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.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
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.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
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.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
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.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
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.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
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.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
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.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
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.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
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.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
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.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
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.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
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.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
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.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
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.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
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.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
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.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
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.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
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.status_error_cor(status_error_cor),
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.status_error_uncor(status_error_uncor)
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);
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endmodule
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`resetall
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