mirror of
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171 lines
10 KiB
Tcl
171 lines
10 KiB
Tcl
# Timing constraints for BittWare 520N-MX
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set_time_format -unit ns -decimal_places 3
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# Clock constraints
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create_clock -name {config_clk} -period 20.000 [ get_ports {config_clk} ]
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create_clock -name {usr_refclk0} -period 3.333 [ get_ports {usr_refclk0} ]
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create_clock -name {usr_refclk1} -period 3.333 [ get_ports {usr_refclk1} ]
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create_clock -name {mem0_refclk} -period 3.333 [ get_ports {mem0_refclk} ]
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create_clock -name {mem1_refclk} -period 3.333 [ get_ports {mem1_refclk} ]
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create_clock -name {esram_0_refclk} -period 5.000 [ get_ports {esram_0_refclk} ]
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create_clock -name {esram_1_refclk} -period 5.000 [ get_ports {esram_1_refclk} ]
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create_clock -name {hbm_top_refclk} -period 5.000 [ get_ports {hbm_top_refclk} ]
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create_clock -name {hbm_bottom_refclk} -period 5.000 [ get_ports {hbm_bottom_refclk} ]
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create_clock -name {pcie_refclk} -period 10.000 [ get_ports {pcie_refclk} ]
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create_clock -name {qsfp0_refclk} -period 1.551 [ get_ports {qsfp0_refclk} ]
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create_clock -name {qsfp1_refclk} -period 1.551 [ get_ports {qsfp1_refclk} ]
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create_clock -name {qsfp2_refclk} -period 1.551 [ get_ports {qsfp2_refclk} ]
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create_clock -name {qsfp3_refclk} -period 1.551 [ get_ports {qsfp3_refclk} ]
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derive_clock_uncertainty
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set_clock_groups -asynchronous -group [ get_clocks {config_clk} ]
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set_clock_groups -asynchronous -group [ get_clocks {usr_refclk0} ]
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set_clock_groups -asynchronous -group [ get_clocks {usr_refclk1} ]
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set_clock_groups -asynchronous -group [ get_clocks {mem0_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {mem1_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {esram_0_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {esram_1_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {hbm_top_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {hbm_bottom_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {pcie_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp2_refclk} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp3_refclk} ]
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# JTAG constraints
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create_clock -name {altera_reserved_tck} -period 62.500 {altera_reserved_tck}
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set_clock_groups -asynchronous -group {altera_reserved_tck}
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# IO constraints
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set_false_path -to "led_user_red[*]"
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set_false_path -to "led_user_grn[*]"
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set_false_path -to "led_qsfp[*]"
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set_false_path -to "uart_rx"
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set_false_path -from "uart_tx"
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set_false_path -to "fpga_i2c_sda"
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set_false_path -from "fpga_i2c_sda"
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set_false_path -to "fpga_i2c_scl"
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set_false_path -from "fpga_i2c_scl"
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set_false_path -to "fpga_i2c_req_l"
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set_false_path -from "fpga_i2c_mux_gnt"
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set_false_path -from "fpga_gpio_1"
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set_false_path -from "fpga_rst_n"
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set_false_path -from "pcie_perstn"
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set_false_path -from "qsfp_irq_n[*]"
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set_false_path -to "oc0_gpio[*]"
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set_false_path -from "oc0_gpio[*]"
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set_false_path -to "oc0_gpio_dir[*]"
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set_false_path -to "oc0_buff_en_n[*]"
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set_false_path -to "oc1_gpio[*]"
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set_false_path -from "oc1_gpio[*]"
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set_false_path -to "oc1_gpio_dir[*]"
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set_false_path -to "oc1_buff_en_n[*]"
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set_false_path -from "oc2_perst_n"
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set_false_path -to "oc2_buff_in_sel"
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set_false_path -from "oc3_perst_n"
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set_false_path -to "oc3_buff_in_sel"
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source ../lib/eth/syn/quartus_pro/eth_mac_fifo.sdc
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source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc
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source ../lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc
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# clocking infrastructure
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constrain_sync_reset_inst "sync_reset_100mhz_inst"
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# PHY clocks
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
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# PHY resets
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
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# 10G MAC
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constrain_eth_mac_fifo_inst "core_inst|eth_mac_10g_fifo_inst"
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constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|rx_fifo|fifo_inst"
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constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|tx_fifo|fifo_inst"
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