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333 lines
12 KiB
Verilog
333 lines
12 KiB
Verilog
/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Ethernet 2 port multiplexer
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*/
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module eth_mux_2
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame inputs
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*/
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input wire input_0_eth_hdr_valid,
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output wire input_0_eth_hdr_ready,
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input wire [47:0] input_0_eth_dest_mac,
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input wire [47:0] input_0_eth_src_mac,
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input wire [15:0] input_0_eth_type,
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input wire [7:0] input_0_eth_payload_tdata,
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input wire input_0_eth_payload_tvalid,
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output wire input_0_eth_payload_tready,
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input wire input_0_eth_payload_tlast,
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input wire input_0_eth_payload_tuser,
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input wire input_1_eth_hdr_valid,
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output wire input_1_eth_hdr_ready,
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input wire [47:0] input_1_eth_dest_mac,
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input wire [47:0] input_1_eth_src_mac,
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input wire [15:0] input_1_eth_type,
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input wire [7:0] input_1_eth_payload_tdata,
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input wire input_1_eth_payload_tvalid,
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output wire input_1_eth_payload_tready,
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input wire input_1_eth_payload_tlast,
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input wire input_1_eth_payload_tuser,
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/*
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* Ethernet frame output
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*/
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output wire output_eth_hdr_valid,
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input wire output_eth_hdr_ready,
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output wire [47:0] output_eth_dest_mac,
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output wire [47:0] output_eth_src_mac,
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output wire [15:0] output_eth_type,
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output wire [7:0] output_eth_payload_tdata,
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output wire output_eth_payload_tvalid,
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input wire output_eth_payload_tready,
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output wire output_eth_payload_tlast,
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output wire output_eth_payload_tuser,
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/*
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* Control
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*/
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input wire enable,
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input wire [0:0] select
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);
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reg [0:0] select_reg = 1'd0, select_next;
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reg frame_reg = 1'b0, frame_next;
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reg input_0_eth_hdr_ready_reg = 1'b0, input_0_eth_hdr_ready_next;
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reg input_1_eth_hdr_ready_reg = 1'b0, input_1_eth_hdr_ready_next;
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reg input_0_eth_payload_tready_reg = 1'b0, input_0_eth_payload_tready_next;
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reg input_1_eth_payload_tready_reg = 1'b0, input_1_eth_payload_tready_next;
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reg output_eth_hdr_valid_reg = 1'b0, output_eth_hdr_valid_next;
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reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
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reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
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reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
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// internal datapath
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reg [7:0] output_eth_payload_tdata_int;
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reg output_eth_payload_tvalid_int;
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reg output_eth_payload_tready_int_reg = 1'b0;
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reg output_eth_payload_tlast_int;
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reg output_eth_payload_tuser_int;
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wire output_eth_payload_tready_int_early;
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assign input_0_eth_hdr_ready = input_0_eth_hdr_ready_reg;
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assign input_1_eth_hdr_ready = input_1_eth_hdr_ready_reg;
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assign input_0_eth_payload_tready = input_0_eth_payload_tready_reg;
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assign input_1_eth_payload_tready = input_1_eth_payload_tready_reg;
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assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
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assign output_eth_dest_mac = output_eth_dest_mac_reg;
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assign output_eth_src_mac = output_eth_src_mac_reg;
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assign output_eth_type = output_eth_type_reg;
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// mux for start of packet detection
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reg selected_input_eth_hdr_valid;
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reg [47:0] selected_input_eth_dest_mac;
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reg [47:0] selected_input_eth_src_mac;
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reg [15:0] selected_input_eth_type;
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always @* begin
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case (select)
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1'd0: begin
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selected_input_eth_hdr_valid = input_0_eth_hdr_valid;
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selected_input_eth_dest_mac = input_0_eth_dest_mac;
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selected_input_eth_src_mac = input_0_eth_src_mac;
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selected_input_eth_type = input_0_eth_type;
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end
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1'd1: begin
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selected_input_eth_hdr_valid = input_1_eth_hdr_valid;
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selected_input_eth_dest_mac = input_1_eth_dest_mac;
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selected_input_eth_src_mac = input_1_eth_src_mac;
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selected_input_eth_type = input_1_eth_type;
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end
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default: begin
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selected_input_eth_hdr_valid = 1'b0;
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selected_input_eth_dest_mac = 48'd0;
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selected_input_eth_src_mac = 48'd0;
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selected_input_eth_type = 16'd0;
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end
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endcase
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end
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// mux for incoming packet
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reg [7:0] current_input_tdata;
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reg current_input_tvalid;
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reg current_input_tready;
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reg current_input_tlast;
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reg current_input_tuser;
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always @* begin
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case (select_reg)
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1'd0: begin
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current_input_tdata = input_0_eth_payload_tdata;
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current_input_tvalid = input_0_eth_payload_tvalid;
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current_input_tready = input_0_eth_payload_tready;
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current_input_tlast = input_0_eth_payload_tlast;
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current_input_tuser = input_0_eth_payload_tuser;
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end
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1'd1: begin
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current_input_tdata = input_1_eth_payload_tdata;
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current_input_tvalid = input_1_eth_payload_tvalid;
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current_input_tready = input_1_eth_payload_tready;
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current_input_tlast = input_1_eth_payload_tlast;
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current_input_tuser = input_1_eth_payload_tuser;
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end
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default: begin
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current_input_tdata = 8'd0;
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current_input_tvalid = 1'b0;
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current_input_tready = 1'b0;
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current_input_tlast = 1'b0;
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current_input_tuser = 1'b0;
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end
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endcase
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end
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always @* begin
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select_next = select_reg;
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frame_next = frame_reg;
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input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_reg & ~input_0_eth_hdr_valid;
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input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_reg & ~input_1_eth_hdr_valid;
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input_0_eth_payload_tready_next = 1'b0;
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input_1_eth_payload_tready_next = 1'b0;
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output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
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output_eth_dest_mac_next = output_eth_dest_mac_reg;
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output_eth_src_mac_next = output_eth_src_mac_reg;
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output_eth_type_next = output_eth_type_reg;
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if (current_input_tvalid & current_input_tready) begin
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// end of frame detection
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if (current_input_tlast) begin
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frame_next = 1'b0;
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end
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end
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if (~frame_reg & enable & ~output_eth_hdr_valid & selected_input_eth_hdr_valid) begin
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// start of frame, grab select value
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frame_next = 1'b1;
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select_next = select;
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case (select_next)
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1'd0: input_0_eth_hdr_ready_next = 1'b1;
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1'd1: input_1_eth_hdr_ready_next = 1'b1;
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endcase
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output_eth_hdr_valid_next = 1'b1;
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output_eth_dest_mac_next = selected_input_eth_dest_mac;
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output_eth_src_mac_next = selected_input_eth_src_mac;
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output_eth_type_next = selected_input_eth_type;
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end
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// generate ready signal on selected port
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case (select_next)
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1'd0: input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
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1'd1: input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
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endcase
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// pass through selected packet data
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output_eth_payload_tdata_int = current_input_tdata;
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output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
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output_eth_payload_tlast_int = current_input_tlast;
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output_eth_payload_tuser_int = current_input_tuser;
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end
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always @(posedge clk) begin
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if (rst) begin
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select_reg <= 1'd0;
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frame_reg <= 1'b0;
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input_0_eth_hdr_ready_reg <= 1'b0;
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input_1_eth_hdr_ready_reg <= 1'b0;
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input_0_eth_payload_tready_reg <= 1'b0;
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input_1_eth_payload_tready_reg <= 1'b0;
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output_eth_hdr_valid_reg <= 1'b0;
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end else begin
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select_reg <= select_next;
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frame_reg <= frame_next;
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input_0_eth_hdr_ready_reg <= input_0_eth_hdr_ready_next;
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input_1_eth_hdr_ready_reg <= input_1_eth_hdr_ready_next;
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input_0_eth_payload_tready_reg <= input_0_eth_payload_tready_next;
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input_1_eth_payload_tready_reg <= input_1_eth_payload_tready_next;
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output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
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end
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output_eth_dest_mac_reg <= output_eth_dest_mac_next;
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output_eth_src_mac_reg <= output_eth_src_mac_next;
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output_eth_type_reg <= output_eth_type_next;
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end
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// output datapath logic
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reg [7:0] output_eth_payload_tdata_reg = 8'd0;
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reg output_eth_payload_tvalid_reg = 1'b0, output_eth_payload_tvalid_next;
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reg output_eth_payload_tlast_reg = 1'b0;
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reg output_eth_payload_tuser_reg = 1'b0;
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reg [7:0] temp_eth_payload_tdata_reg = 8'd0;
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reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
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reg temp_eth_payload_tlast_reg = 1'b0;
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reg temp_eth_payload_tuser_reg = 1'b0;
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// datapath control
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reg store_eth_payload_int_to_output;
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reg store_eth_payload_int_to_temp;
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reg store_eth_payload_temp_to_output;
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assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
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assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
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assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
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assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & (~output_eth_payload_tvalid_reg | ~output_eth_payload_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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output_eth_payload_tvalid_next = output_eth_payload_tvalid_reg;
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temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
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store_eth_payload_int_to_output = 1'b0;
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store_eth_payload_int_to_temp = 1'b0;
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store_eth_payload_temp_to_output = 1'b0;
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if (output_eth_payload_tready_int_reg) begin
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// input is ready
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if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
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store_eth_payload_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
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store_eth_payload_int_to_temp = 1'b1;
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end
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end else if (output_eth_payload_tready) begin
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// input is not ready, but output is ready
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output_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
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temp_eth_payload_tvalid_next = 1'b0;
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store_eth_payload_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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output_eth_payload_tvalid_reg <= 1'b0;
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output_eth_payload_tready_int_reg <= 1'b0;
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temp_eth_payload_tvalid_reg <= 1'b0;
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end else begin
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output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_next;
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output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
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temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
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end
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// datapath
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if (store_eth_payload_int_to_output) begin
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output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
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output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
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output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
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end else if (store_eth_payload_temp_to_output) begin
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output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
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output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
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output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
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end
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if (store_eth_payload_int_to_temp) begin
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temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
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temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
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temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
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end
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end
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endmodule
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