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445 lines
16 KiB
Verilog
445 lines
16 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Ultrascale PCIe AXI DMA
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*/
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module pcie_us_axi_dma #
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(
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// Width of PCIe AXI stream interfaces in bits
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parameter AXIS_PCIE_DATA_WIDTH = 256,
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// PCIe AXI stream tkeep signal width (words per cycle)
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parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
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// PCIe AXI stream RC tuser signal width
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parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
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// PCIe AXI stream RQ tuser signal width
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parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
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// RQ sequence number width
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parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
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// RQ sequence number tracking enable
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parameter RQ_SEQ_NUM_ENABLE = 0,
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// Width of AXI data bus in bits
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parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
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// Width of AXI address bus in bits
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parameter AXI_ADDR_WIDTH = 64,
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// Width of AXI wstrb (width of data bus in words)
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parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
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// Width of AXI ID signal
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parameter AXI_ID_WIDTH = 8,
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// Maximum AXI burst length to generate
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parameter AXI_MAX_BURST_LEN = 256,
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// PCIe address width
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parameter PCIE_ADDR_WIDTH = 64,
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// PCIe tag count
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parameter PCIE_TAG_COUNT = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 64 : 256,
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// PCIe tag field width
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parameter PCIE_TAG_WIDTH = $clog2(PCIE_TAG_COUNT),
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// Support PCIe extended tags
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parameter PCIE_EXT_TAG_ENABLE = (PCIE_TAG_COUNT>32),
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// Length field width
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parameter LEN_WIDTH = 20,
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// Tag field width
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parameter TAG_WIDTH = 8,
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// Operation table size (read)
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parameter READ_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH < PCIE_TAG_WIDTH ? AXI_ID_WIDTH : PCIE_TAG_WIDTH),
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// In-flight transmit limit (read)
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parameter READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
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// Transmit flow control (read)
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parameter READ_TX_FC_ENABLE = 0,
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// Operation table size (write)
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parameter WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1),
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// In-flight transmit limit (write)
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parameter WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
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// Transmit flow control (write)
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parameter WRITE_TX_FC_ENABLE = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input (RC)
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*/
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input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
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input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
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input wire s_axis_rc_tvalid,
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output wire s_axis_rc_tready,
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input wire s_axis_rc_tlast,
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input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
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/*
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* AXI output (RQ)
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*/
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output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
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output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
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output wire m_axis_rq_tvalid,
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input wire m_axis_rq_tready,
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output wire m_axis_rq_tlast,
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output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
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/*
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* Transmit sequence number input
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*/
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input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0,
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input wire s_axis_rq_seq_num_valid_0,
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input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1,
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input wire s_axis_rq_seq_num_valid_1,
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/*
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* Transmit flow control
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*/
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input wire [7:0] pcie_tx_fc_nph_av,
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input wire [7:0] pcie_tx_fc_ph_av,
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input wire [11:0] pcie_tx_fc_pd_av,
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/*
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* AXI read descriptor input
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*/
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input wire [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr,
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input wire [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr,
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input wire [LEN_WIDTH-1:0] s_axis_read_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_read_desc_tag,
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input wire s_axis_read_desc_valid,
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output wire s_axis_read_desc_ready,
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/*
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* AXI read descriptor status output
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*/
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output wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag,
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output wire m_axis_read_desc_status_valid,
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/*
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* AXI write descriptor input
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*/
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input wire [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr,
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input wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr,
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input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
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input wire s_axis_write_desc_valid,
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output wire s_axis_write_desc_ready,
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/*
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* AXI write descriptor status output
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*/
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output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
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output wire m_axis_write_desc_status_valid,
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/*
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* AXI master interface
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*/
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output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arlock,
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output wire [3:0] m_axi_arcache,
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output wire [2:0] m_axi_arprot,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire m_axi_rvalid,
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output wire m_axi_rready,
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/*
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* Configuration
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*/
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input wire read_enable,
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input wire write_enable,
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input wire ext_tag_enable,
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input wire [15:0] requester_id,
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input wire requester_id_enable,
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input wire [2:0] max_read_request_size,
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input wire [2:0] max_payload_size,
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/*
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* Status
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*/
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output wire status_error_cor,
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output wire status_error_uncor
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);
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wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata_read;
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wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep_read;
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wire axis_rq_tvalid_read;
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wire axis_rq_tready_read;
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wire axis_rq_tlast_read;
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wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser_read;
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wire [RQ_SEQ_NUM_WIDTH-1:0] axis_rq_seq_num_read_0;
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wire axis_rq_seq_num_valid_read_0;
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wire [RQ_SEQ_NUM_WIDTH-1:0] axis_rq_seq_num_read_1;
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wire axis_rq_seq_num_valid_read_1;
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pcie_us_axi_dma_rd #(
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.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
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.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
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.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
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.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
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.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
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.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
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.AXI_ID_WIDTH(AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
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.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
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.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
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.PCIE_TAG_WIDTH(PCIE_TAG_WIDTH),
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.PCIE_EXT_TAG_ENABLE(PCIE_EXT_TAG_ENABLE),
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.LEN_WIDTH(LEN_WIDTH),
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.TAG_WIDTH(TAG_WIDTH),
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.OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
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.TX_LIMIT(READ_TX_LIMIT),
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.TX_FC_ENABLE(READ_TX_FC_ENABLE)
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)
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pcie_us_axi_dma_rd_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI input (RC)
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*/
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.s_axis_rc_tdata(s_axis_rc_tdata),
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.s_axis_rc_tkeep(s_axis_rc_tkeep),
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.s_axis_rc_tvalid(s_axis_rc_tvalid),
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.s_axis_rc_tready(s_axis_rc_tready),
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.s_axis_rc_tlast(s_axis_rc_tlast),
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.s_axis_rc_tuser(s_axis_rc_tuser),
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/*
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* AXI output (RQ)
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*/
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.m_axis_rq_tdata(axis_rq_tdata_read),
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.m_axis_rq_tkeep(axis_rq_tkeep_read),
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.m_axis_rq_tvalid(axis_rq_tvalid_read),
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.m_axis_rq_tready(axis_rq_tready_read),
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.m_axis_rq_tlast(axis_rq_tlast_read),
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.m_axis_rq_tuser(axis_rq_tuser_read),
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/*
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* Transmit sequence number input
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*/
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.s_axis_rq_seq_num_0(axis_rq_seq_num_read_0),
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.s_axis_rq_seq_num_valid_0(axis_rq_seq_num_valid_read_0),
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.s_axis_rq_seq_num_1(axis_rq_seq_num_read_1),
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.s_axis_rq_seq_num_valid_1(axis_rq_seq_num_valid_read_1),
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/*
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* Transmit flow control
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*/
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.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
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/*
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* AXI read descriptor input
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*/
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.s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr),
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.s_axis_read_desc_axi_addr(s_axis_read_desc_axi_addr),
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.s_axis_read_desc_len(s_axis_read_desc_len),
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.s_axis_read_desc_tag(s_axis_read_desc_tag),
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.s_axis_read_desc_valid(s_axis_read_desc_valid),
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.s_axis_read_desc_ready(s_axis_read_desc_ready),
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/*
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* AXI read descriptor status output
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*/
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.m_axis_read_desc_status_tag(m_axis_read_desc_status_tag),
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.m_axis_read_desc_status_valid(m_axis_read_desc_status_valid),
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/*
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* AXI master interface
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*/
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.m_axi_awid(m_axi_awid),
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.m_axi_awaddr(m_axi_awaddr),
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.m_axi_awlen(m_axi_awlen),
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.m_axi_awsize(m_axi_awsize),
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.m_axi_awburst(m_axi_awburst),
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.m_axi_awlock(m_axi_awlock),
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.m_axi_awcache(m_axi_awcache),
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.m_axi_awprot(m_axi_awprot),
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.m_axi_awvalid(m_axi_awvalid),
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.m_axi_awready(m_axi_awready),
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.m_axi_wdata(m_axi_wdata),
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.m_axi_wstrb(m_axi_wstrb),
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.m_axi_wlast(m_axi_wlast),
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.m_axi_wvalid(m_axi_wvalid),
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.m_axi_wready(m_axi_wready),
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.m_axi_bid(m_axi_bid),
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.m_axi_bresp(m_axi_bresp),
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.m_axi_bvalid(m_axi_bvalid),
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.m_axi_bready(m_axi_bready),
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/*
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* Configuration
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*/
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.enable(read_enable),
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.ext_tag_enable(ext_tag_enable),
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.requester_id(requester_id),
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.requester_id_enable(requester_id_enable),
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.max_read_request_size(max_read_request_size),
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/*
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* Status
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*/
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.status_error_cor(status_error_cor),
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.status_error_uncor(status_error_uncor)
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);
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pcie_us_axi_dma_wr #(
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.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
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.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
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.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
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.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
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.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
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.AXI_ID_WIDTH(AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
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.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
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.LEN_WIDTH(LEN_WIDTH),
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.TAG_WIDTH(TAG_WIDTH),
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.OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
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.TX_LIMIT(WRITE_TX_LIMIT),
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.TX_FC_ENABLE(WRITE_TX_FC_ENABLE)
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)
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pcie_us_axi_dma_wr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI input (RQ from read DMA)
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*/
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.s_axis_rq_tdata(axis_rq_tdata_read),
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.s_axis_rq_tkeep(axis_rq_tkeep_read),
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.s_axis_rq_tvalid(axis_rq_tvalid_read),
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.s_axis_rq_tready(axis_rq_tready_read),
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.s_axis_rq_tlast(axis_rq_tlast_read),
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.s_axis_rq_tuser(axis_rq_tuser_read),
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/*
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* AXI output (RQ)
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*/
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.m_axis_rq_tdata(m_axis_rq_tdata),
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.m_axis_rq_tkeep(m_axis_rq_tkeep),
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.m_axis_rq_tvalid(m_axis_rq_tvalid),
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.m_axis_rq_tready(m_axis_rq_tready),
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.m_axis_rq_tlast(m_axis_rq_tlast),
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.m_axis_rq_tuser(m_axis_rq_tuser),
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/*
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* Transmit sequence number input
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*/
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.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
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.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
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.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
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.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
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/*
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* Transmit sequence number output (to read DMA)
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*/
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.m_axis_rq_seq_num_0(axis_rq_seq_num_read_0),
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.m_axis_rq_seq_num_valid_0(axis_rq_seq_num_valid_read_0),
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.m_axis_rq_seq_num_1(axis_rq_seq_num_read_1),
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.m_axis_rq_seq_num_valid_1(axis_rq_seq_num_valid_read_1),
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/*
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* Transmit flow control
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*/
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.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
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.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
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/*
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* AXI write descriptor input
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*/
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.s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr),
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.s_axis_write_desc_axi_addr(s_axis_write_desc_axi_addr),
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.s_axis_write_desc_len(s_axis_write_desc_len),
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.s_axis_write_desc_tag(s_axis_write_desc_tag),
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.s_axis_write_desc_valid(s_axis_write_desc_valid),
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.s_axis_write_desc_ready(s_axis_write_desc_ready),
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/*
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* AXI write descriptor status output
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*/
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.m_axis_write_desc_status_tag(m_axis_write_desc_status_tag),
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.m_axis_write_desc_status_valid(m_axis_write_desc_status_valid),
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/*
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* AXI master interface
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*/
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.m_axi_arid(m_axi_arid),
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.m_axi_araddr(m_axi_araddr),
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.m_axi_arlen(m_axi_arlen),
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|
.m_axi_arsize(m_axi_arsize),
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|
.m_axi_arburst(m_axi_arburst),
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.m_axi_arlock(m_axi_arlock),
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.m_axi_arcache(m_axi_arcache),
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.m_axi_arprot(m_axi_arprot),
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|
.m_axi_arvalid(m_axi_arvalid),
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|
.m_axi_arready(m_axi_arready),
|
|
.m_axi_rid(m_axi_rid),
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|
.m_axi_rdata(m_axi_rdata),
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|
.m_axi_rresp(m_axi_rresp),
|
|
.m_axi_rlast(m_axi_rlast),
|
|
.m_axi_rvalid(m_axi_rvalid),
|
|
.m_axi_rready(m_axi_rready),
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|
|
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/*
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* Configuration
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*/
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.enable(write_enable),
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.requester_id(requester_id),
|
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.requester_id_enable(requester_id_enable),
|
|
.max_payload_size(max_payload_size)
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|
);
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|
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endmodule
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