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253 lines
7.4 KiB
Verilog
253 lines
7.4 KiB
Verilog
/*
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Copyright (c) 2015-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* 10G Ethernet MAC
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*/
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module eth_mac_10g #
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(
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parameter DATA_WIDTH = 64,
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter CTRL_WIDTH = (DATA_WIDTH/8),
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parameter ENABLE_PADDING = 1,
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parameter ENABLE_DIC = 1,
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parameter MIN_FRAME_LENGTH = 64,
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parameter PTP_PERIOD_NS = 4'h6,
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parameter PTP_PERIOD_FNS = 16'h6666,
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parameter TX_PTP_TS_ENABLE = 0,
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parameter TX_PTP_TS_WIDTH = 96,
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parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
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parameter TX_PTP_TAG_WIDTH = 16,
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parameter RX_PTP_TS_ENABLE = 0,
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parameter RX_PTP_TS_WIDTH = 96,
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parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
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parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
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)
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(
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input wire rx_clk,
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input wire rx_rst,
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input wire tx_clk,
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input wire tx_rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] tx_axis_tdata,
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input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
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input wire tx_axis_tvalid,
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output wire tx_axis_tready,
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input wire tx_axis_tlast,
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input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] rx_axis_tdata,
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output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
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output wire rx_axis_tvalid,
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output wire rx_axis_tlast,
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output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
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/*
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* XGMII interface
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*/
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input wire [DATA_WIDTH-1:0] xgmii_rxd,
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input wire [CTRL_WIDTH-1:0] xgmii_rxc,
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output wire [DATA_WIDTH-1:0] xgmii_txd,
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output wire [CTRL_WIDTH-1:0] xgmii_txc,
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/*
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* PTP
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*/
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input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
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input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
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output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
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output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
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output wire tx_axis_ptp_ts_valid,
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/*
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* Status
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*/
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output wire [1:0] tx_start_packet,
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output wire tx_error_underflow,
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output wire [1:0] rx_start_packet,
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output wire rx_error_bad_frame,
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output wire rx_error_bad_fcs,
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/*
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* Configuration
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*/
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input wire [7:0] ifg_delay
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);
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// bus width assertions
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initial begin
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if (DATA_WIDTH != 32 && DATA_WIDTH != 64) begin
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$error("Error: Interface width must be 32 or 64");
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$finish;
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end
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if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
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$error("Error: Interface requires byte (8-bit) granularity");
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$finish;
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end
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end
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generate
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if (DATA_WIDTH == 64) begin
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axis_xgmii_rx_64 #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_WIDTH(KEEP_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.PTP_PERIOD_NS(PTP_PERIOD_NS),
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.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
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.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
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.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
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.USER_WIDTH(RX_USER_WIDTH)
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)
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axis_xgmii_rx_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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.m_axis_tdata(rx_axis_tdata),
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.m_axis_tkeep(rx_axis_tkeep),
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.m_axis_tvalid(rx_axis_tvalid),
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.m_axis_tlast(rx_axis_tlast),
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.m_axis_tuser(rx_axis_tuser),
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.ptp_ts(rx_ptp_ts),
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.start_packet(rx_start_packet),
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.error_bad_frame(rx_error_bad_frame),
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.error_bad_fcs(rx_error_bad_fcs)
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);
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axis_xgmii_tx_64 #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_WIDTH(KEEP_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.ENABLE_PADDING(ENABLE_PADDING),
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.ENABLE_DIC(ENABLE_DIC),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
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.PTP_PERIOD_NS(PTP_PERIOD_NS),
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.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
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.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
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.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
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.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
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.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
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.USER_WIDTH(TX_USER_WIDTH)
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)
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axis_xgmii_tx_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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.s_axis_tdata(tx_axis_tdata),
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.s_axis_tkeep(tx_axis_tkeep),
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.s_axis_tvalid(tx_axis_tvalid),
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.s_axis_tready(tx_axis_tready),
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.s_axis_tlast(tx_axis_tlast),
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.s_axis_tuser(tx_axis_tuser),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.ptp_ts(tx_ptp_ts),
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.m_axis_ptp_ts(tx_axis_ptp_ts),
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.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
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.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
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.ifg_delay(ifg_delay),
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.start_packet(tx_start_packet),
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.error_underflow(tx_error_underflow)
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);
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end else begin
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axis_xgmii_rx_32 #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_WIDTH(KEEP_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
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.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
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.USER_WIDTH(RX_USER_WIDTH)
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)
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axis_xgmii_rx_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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.m_axis_tdata(rx_axis_tdata),
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.m_axis_tkeep(rx_axis_tkeep),
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.m_axis_tvalid(rx_axis_tvalid),
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.m_axis_tlast(rx_axis_tlast),
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.m_axis_tuser(rx_axis_tuser),
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.ptp_ts(rx_ptp_ts),
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.start_packet(rx_start_packet[0]),
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.error_bad_frame(rx_error_bad_frame),
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.error_bad_fcs(rx_error_bad_fcs)
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);
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assign rx_start_packet[1] = 1'b0;
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axis_xgmii_tx_32 #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_WIDTH(KEEP_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.ENABLE_PADDING(ENABLE_PADDING),
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.ENABLE_DIC(ENABLE_DIC),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
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.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
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.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
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.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
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.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
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.USER_WIDTH(TX_USER_WIDTH)
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)
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axis_xgmii_tx_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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.s_axis_tdata(tx_axis_tdata),
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.s_axis_tkeep(tx_axis_tkeep),
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.s_axis_tvalid(tx_axis_tvalid),
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.s_axis_tready(tx_axis_tready),
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.s_axis_tlast(tx_axis_tlast),
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.s_axis_tuser(tx_axis_tuser),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.ptp_ts(tx_ptp_ts),
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.m_axis_ptp_ts(tx_axis_ptp_ts),
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.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
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.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
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.ifg_delay(ifg_delay),
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.start_packet(tx_start_packet[0])
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);
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assign tx_start_packet[1] = 1'b0;
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end
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endgenerate
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endmodule
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