Alex Forencich 7d2f77a30b fpga/common: Connect xcvr_ctrl_rst to QPLLs ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2023-07-17 18:44:42 -07:00

..

rtl

fpga/common: Connect xcvr_ctrl_rst to QPLLs

2023-07-17 18:44:42 -07:00

syn/vivado

fpga/common: Fix GT wrapper timing constraints when DRP interface is tied off

2023-07-17 18:43:07 -07:00

tb

Consolidate CQs

2023-07-10 17:52:34 -07:00

lib

Add symlink

2019-08-11 00:33:22 -07:00