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FPGA
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corundum
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corundum
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example
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S10DX_DK
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fpga_10g
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rtl
History
Alex Forencich
1be196279f
Fix FIFO instances in S10DX example design
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-17 11:05:24 -07:00
..
avst2axis.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
axis2avst.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
debounce_switch.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_mac_quad_wrapper.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
fpga_core.v
Fix FIFO instances in S10DX example design
2023-07-17 11:05:24 -07:00
fpga.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
sync_signal.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
xcvr_ctrl.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
