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https://github.com/corundum/corundum.git
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142 lines
3.7 KiB
Verilog
142 lines
3.7 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* MII PHY interface
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*/
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module mii_phy_if #
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(
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// target ("SIM", "GENERIC", "XILINX", "ALTERA")
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parameter TARGET = "GENERIC",
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// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
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// Use BUFR for Virtex-5, Virtex-6, 7-series
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// Use BUFG for Ultrascale
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// Use BUFIO2 for Spartan-6
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parameter CLOCK_INPUT_STYLE = "BUFIO2"
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)
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(
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input wire rst,
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/*
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* MII interface to MAC
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*/
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output wire mac_mii_rx_clk,
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output wire mac_mii_rx_rst,
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output wire [3:0] mac_mii_rxd,
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output wire mac_mii_rx_dv,
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output wire mac_mii_rx_er,
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output wire mac_mii_tx_clk,
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output wire mac_mii_tx_rst,
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input wire [3:0] mac_mii_txd,
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input wire mac_mii_tx_en,
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input wire mac_mii_tx_er,
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/*
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* MII interface to PHY
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*/
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input wire phy_mii_rx_clk,
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input wire [3:0] phy_mii_rxd,
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input wire phy_mii_rx_dv,
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input wire phy_mii_rx_er,
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input wire phy_mii_tx_clk,
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output wire [3:0] phy_mii_txd,
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output wire phy_mii_tx_en,
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output wire phy_mii_tx_er
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);
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ssio_sdr_in #
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(
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.TARGET(TARGET),
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.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
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.WIDTH(6)
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)
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rx_ssio_sdr_inst (
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.input_clk(phy_mii_rx_clk),
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.input_d({phy_mii_rxd, phy_mii_rx_dv, phy_mii_rx_er}),
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.output_clk(mac_mii_rx_clk),
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.output_q({mac_mii_rxd, mac_mii_rx_dv, mac_mii_rx_er})
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);
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(* IOB = "TRUE" *)
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reg [3:0] phy_mii_txd_reg = 4'd0;
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(* IOB = "TRUE" *)
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reg phy_mii_tx_en_reg = 1'b0, phy_mii_tx_er_reg = 1'b0;
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assign phy_mii_txd = phy_mii_txd_reg;
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assign phy_mii_tx_en = phy_mii_tx_en_reg;
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assign phy_mii_tx_er = phy_mii_tx_er_reg;
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always @(posedge mac_mii_tx_clk) begin
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phy_mii_txd_reg <= mac_mii_txd;
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phy_mii_tx_en_reg <= mac_mii_tx_en;
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phy_mii_tx_er_reg <= mac_mii_tx_er;
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end
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generate
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if (TARGET == "XILINX") begin
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BUFG
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mii_bufg_inst (
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.I(phy_mii_tx_clk),
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.O(mac_mii_tx_clk)
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);
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end else begin
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assign mac_mii_tx_clk = phy_mii_tx_clk;
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end
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endgenerate
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// reset sync
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reg [3:0] tx_rst_reg = 4'hf;
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assign mac_mii_tx_rst = tx_rst_reg[0];
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always @(posedge mac_mii_tx_clk or posedge rst) begin
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if (rst) begin
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tx_rst_reg <= 4'hf;
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end else begin
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tx_rst_reg <= {1'b0, tx_rst_reg[3:1]};
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end
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end
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reg [3:0] rx_rst_reg = 4'hf;
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assign mac_mii_rx_rst = rx_rst_reg[0];
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always @(posedge mac_mii_rx_clk or posedge rst) begin
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if (rst) begin
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rx_rst_reg <= 4'hf;
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end else begin
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rx_rst_reg <= {1'b0, rx_rst_reg[3:1]};
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end
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end
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endmodule
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`resetall
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